公开(公告)号：CA2065989C

公开(公告)日：1998-03-31

申请号：CA2065989

申请日：1992-04-14

Applicant: IBM

Inventor： KEENER DON STEVEN ,  VOORHEES RICHARD W ,  MOORE GREGORY JAMES

IPC: G06F13/38 ,  G06F13/28 ,  G06F12/00 ,  G06F13/14

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory. The processor device and storage controller cooperate for exchange of blocks of data between the local processor bus and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus as necessary.

公开(公告)号：IN186098B

公开(公告)日：2001-06-16

申请号：IN363DE1993

申请日：1993-04-13

Applicant: IBM

Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  SCHEIERN KEVIN LEE ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

IPC: G06F13/38

公开(公告)号：CA2092631A1

公开(公告)日：1993-12-20

申请号：CA2092631

申请日：1993-03-12

Applicant: IBM

Inventor： KEENER DON S ,  MCNEILL ANDREW B ,  SCHEIERN KEVIN L ,  NEWSOM THOMAS H ,  VOORHEES RICHARD W ,  WACHTEL EDWARD I

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/16

Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

公开(公告)号：PH26617A

公开(公告)日：1992-08-19

申请号：PH39656

申请日：1989-12-08

Applicant: IBM

Inventor： BUSH GREGORY F ,  KEENER DON S ,  MOREZ JEANNE E ,  VOORHEES RICHARD W

IPC: G06F12/06 ,  G06F12/00

Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

公开(公告)号：AU623457B2

公开(公告)日：1992-05-14

申请号：AU4609089

申请日：1989-12-08

Applicant: IBM

Inventor： BUSH GREGORY FREDERICK ,  KEENER DON STEVEN ,  MOREL JEANNE ELLEN ,  VOORHEES RICHARD W

IPC: G06F12/06 ,  G06F12/00

Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

公开(公告)号：CA2000009A1

公开(公告)日：1990-06-09

申请号：CA2000009

申请日：1989-10-02

Applicant: IBM

Inventor： BUSH GREGORY F ,  KEENER DON S ,  MOREL JEANNE E ,  VOORHEES RICHARD W

IPC: G06F12/06

Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

公开(公告)号：SG42891A1

公开(公告)日：1997-10-17

申请号：SG1996000456

申请日：1993-05-04

Applicant: IBM

Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  SCHEIERN KEVIN LEE ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

IPC: G06F13/40 ,  G06F13/36

Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

公开(公告)号：CA2065989A1

公开(公告)日：1992-12-08

申请号：CA2065989

申请日：1992-04-14

Applicant: IBM

Inventor： KEENER DON S ,  MOORE GREGORY J ,  VOORHEES RICHARD W

IPC: G06F13/38 ,  G06F13/28 ,  G06F12/00 ,  G06F13/14

Abstract: This invention relates to computers, and more particularly to a storage controller for a computer. The small computer systems interface (SCSI) controller is coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer 10 system has a high speed local processor data bus 34, at least one logical processor device 32 coupled directly to the local processor bus 34 and capable of signalling through the local processor bus 34 an occurrence of the transfer of blocks of data, and a storage controller 40 coupled directly to the local processor bus 34 for regulating communications between the processor device 32 and storage memory devices 36. The storage controller 40 has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus 34 and is capable of signalling through the local processor bus 34 the state of the FIFO memory. The processor device 32 and storage controller 40 cooperate for exchange of blocks of data between the local processor bus 34 and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus 34 as necessary.

公开(公告)号：CA2092631C

公开(公告)日：1997-04-08

申请号：CA2092631

申请日：1993-03-12

Applicant: IBM

Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  SCHEIERN KEVIN LEE ,  NEWSOM THOMAS HAROLD ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/16

Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

公开(公告)号：IN177066B

公开(公告)日：1996-10-26

申请号：IN603DE1990

申请日：1990-06-20

Applicant: IBM

Inventor： BUSH GREGORY FREDERICK ,  KEENER DON STEVEN ,  MOREL JEANNE ELLEN ,  VOORHEES RICHARD W

IPC: G06C1/00 ,  G06C9/00 ,  G06C13/00 ,  G06C15/00