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    Binary arithmetic and logic manipulator
    1.
    发明授权
    Binary arithmetic and logic manipulator 失效
    二进制算术和逻辑操纵器

    公开(公告)号：US3584205A

    公开(公告)日：1971-06-08

    申请号：US3584205D

    申请日：1968-10-14

    Applicant: IBM

    Inventor： MALABY DAVEY ,  WESLEY MICHAEL A

    IPC: G06F7/00 ,  G06F7/02 ,  G06F7/575 ,  H03K19/177 ,  G06F7/38

    CPC classification number: G06F7/575 ,  G06F7/00 ,  G06F7/02 ,  H03K19/17704 ,  H03K19/17728

    Abstract: A programmable binary arithmetic and logic manipulator which comprises a rectangular array of (M) (N+1) logic cells and N+1 columnar control cells. The columnar control cells are designated as U and V and are binary stages capable of assuming binary one or binary zero states. These columnar control cells control the overall operation performed by each column. Associated with each cell are a pair of binary stages designated X and Y respectively, which in conjunction with the columnar control cells U and V define the outputs D and E of a cell as functions of the cell inputs A, B and C. The output lines D and E of each cell are used as inputs to adjacent cells or, at the edges of the array, as inputs to external logic or additional arrays. Each column can be selected by a storage position U as an arithmetic or logical operation. In addition, each column can be selected by a storage position V as (1) their AND and OR function when used with U as a logical operation or (2) as a binary input to the column when used with U as an arithmetic operation. Input C may be connected externally to input B or may instead be connected externally to another array or to external logic. Each logical cell contains a circuit whereby the logic statements for each output line are as follows: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X (UV+UC+UC) (YB+YB))+(UC(YB+YB)) +(UVC

    Data compaction using variable-length coding
    2.
    发明授权
    Data compaction using variable-length coding 失效
    使用可变长度编码进行数据压缩

    公开(公告)号：US3675212A

    公开(公告)日：1972-07-04

    申请号：US3675212D

    申请日：1970-08-10

    Applicant: IBM

    Inventor： RAVIV JOSEF ,  WESLEY MICHAEL A

    IPC: H03M5/00 ,  H03M7/42 ,  G06F5/00 ,  H03K13/00

    CPC classification number: H03M7/42 ,  H03M5/00

    Abstract: A three-state associative memory is employed as an encodingdecoding instrumentality for making conversions between fixedlength codes and variable-length codes. During the encoding process, associations are performed upon fixed-length codes to find the corresponding variable-length codes. The shorter-length codes are assigned to the most frequently occurring words or bytes for achieving a minimum average code length. The available variable-length codes are stored in a field of the associative memory that has uniform word lengths. Memory cells which are not needed for storing bits of the variable-length codes are set to a ''''don''t care'''' state. During each readout of a variable-length code, a corresponding ''''length'''' value is read out of the memory to indicate the number of valid bits that are to be read serially from the data register, excluding the ''''don''t cares.'''' During the decoding process, the bits of successive variable-length codes are fed serially to an argument register, and as each association is performed upon a variable-length code to find the corresponding fixed-length code, the ''''length'''' field indicates the number of bit positions by which the contents of the argument register are to be shifted for bringing the next variable-length code bit string into registry.

    Abstract translation: 采用三状态关联存储器作为在固定长度代码和可变长度代码之间进行转换的编码解码工具。 在编码过程中，以固定长度的代码执行关联，以找到相应的可变长度代码。 较短的代码被分配给最常出现的字或字节，以达到最小的平均代码长度。 可用的可变长度代码存储在具有统一字长的关联存储器的字段中。 将存储可变长度代码的位不需要的存储单元设置为“无关”状态。 在可变长度代码的每次读出期间，从存储器中读出对应的“长度”值，以指示要从数据寄存器串行读取的有效位的数量，不包括“不关心”。 在解码过程中，连续的可变长度码的位被串行地馈送到自变量寄存器，并且当根据可变长度代码执行每个关联以找到对应的固定长度代码时，“长度”字段表示数字 的比特位置，通过该比特位置，参数寄存器的内容将被移位，以使下一个可变长度代码位串进入注册表。

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