公开(公告)号：US3584205A

公开(公告)日：1971-06-08

申请号：US3584205D

申请日：1968-10-14

Applicant: IBM

Inventor： MALABY DAVEY ,  WESLEY MICHAEL A

IPC: G06F7/00 ,  G06F7/02 ,  G06F7/575 ,  H03K19/177 ,  G06F7/38

CPC classification number: G06F7/575 ,  G06F7/00 ,  G06F7/02 ,  H03K19/17704 ,  H03K19/17728

Abstract: A programmable binary arithmetic and logic manipulator which comprises a rectangular array of (M) (N+1) logic cells and N+1 columnar control cells. The columnar control cells are designated as U and V and are binary stages capable of assuming binary one or binary zero states. These columnar control cells control the overall operation performed by each column. Associated with each cell are a pair of binary stages designated X and Y respectively, which in conjunction with the columnar control cells U and V define the outputs D and E of a cell as functions of the cell inputs A, B and C. The output lines D and E of each cell are used as inputs to adjacent cells or, at the edges of the array, as inputs to external logic or additional arrays. Each column can be selected by a storage position U as an arithmetic or logical operation. In addition, each column can be selected by a storage position V as (1) their AND and OR function when used with U as a logical operation or (2) as a binary input to the column when used with U as an arithmetic operation. Input C may be connected externally to input B or may instead be connected externally to another array or to external logic. Each logical cell contains a circuit whereby the logic statements for each output line are as follows: D X(YC+YB)+X(UA+UC(YB+YB)) E X(YB+YC)+X (UV+UC+UC) (YB+YB))+(UC(YB+YB)) +(UVC