公开(公告)号：DE3688580D1

公开(公告)日：1993-07-22

申请号：DE3688580

申请日：1986-09-23

Applicant: IBM

Inventor： YOFFA ELLEN JUNE ,  HAUGE PETER SWIFT

IPC: H01L21/8234 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/088 ,  H03K19/173 ,  G06F15/60

Abstract: A method for increasing the wirability of complementary metal oxide semiconductor (CMOS) differential cascode voltage switch (DCVS) logic circuits which comprises designing the circuitry to permit as many of the internal tree connections as possible to be wired using diffusion techniques. The method utilizes differential pair and load microblocks which have been designed so as to allow mirroring on a vertical centre line. Utilizing the availability of mirroring for individual pairs plus relocation of individual pairs in the logic tree the crossings may be largely eliminated in a shortened period. It utilizes a step by step row and column analysis of the initial or starting tree design resulting from the basic Boolean logic to be performed by the particular circuit and makes required load mirroring and differential pair relocation decisions in an iterative process.

公开(公告)号：DE3688580T2

公开(公告)日：1993-12-23

申请号：DE3688580

申请日：1986-09-23

Applicant: IBM

Inventor： YOFFA ELLEN JUNE ,  HAUGE PETER SWIFT

IPC: H01L21/8234 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/088 ,  H03K19/173 ,  G06F15/60

Abstract: A method for increasing the wirability of complementary metal oxide semiconductor (CMOS) differential cascode voltage switch (DCVS) logic circuits which comprises designing the circuitry to permit as many of the internal tree connections as possible to be wired using diffusion techniques. The method utilizes differential pair and load microblocks which have been designed so as to allow mirroring on a vertical centre line. Utilizing the availability of mirroring for individual pairs plus relocation of individual pairs in the logic tree the crossings may be largely eliminated in a shortened period. It utilizes a step by step row and column analysis of the initial or starting tree design resulting from the basic Boolean logic to be performed by the particular circuit and makes required load mirroring and differential pair relocation decisions in an iterative process.