公开(公告)号：DE3069316D1

公开(公告)日：1984-10-31

申请号：DE3069316

申请日：1980-12-04

Applicant: IBM

Inventor： ZBROZEK JOHN DENNIS

IPC: G11C17/00 ,  G11C7/12 ,  G11C7/14 ,  G11C11/401 ,  G11C11/417 ,  G11C17/12 ,  G11C17/18 ,  G11C7/00

Abstract: For signal storage systems that interrogate a storage cell with a concomitant precharging of the cell signal line (10) non-linear capacitors (40) are employed to provide automatic selective coupling of the respective signal line to a detector (200) for determination of the cell state. By connecting a plurality of signal lines to a detector through respective non-linear capacitors that assume a significantly enlarged capacitance when the precharge voltage level is asserted, enhanced coupling of the signal line may be achieved and by selectively precharging the signal line to be interrogated, no triggering of enlarged capacitance at other signal lines occurs to load the detection system. A symmetrical configuration for use with a reference comparison type of detection, may be provided. A special reference circuit (206) using a pair of joined signal lines provides a ramp signal having intermediate voltage values relative to the state-indicative signals produced by interrogated cells for the two respective cell states. By using a symmetrical configuration and a reference circuit with the same devices as the storage circuitry any shifts in characteristics as a result of manufacturing variations tend to cancel in the detection.

公开(公告)号：DE3485686D1

公开(公告)日：1992-06-04

申请号：DE3485686

申请日：1984-12-18

Applicant: IBM

Inventor： CHEEK ELBERT ALSTON ,  THOMAS DAVID ROSS ,  ZBROZEK JOHN DENNIS

IPC: G11C29/04 ,  G06F9/06 ,  G06F9/445 ,  G06F12/06 ,  G11C17/00 ,  G06F11/20

Abstract: Data from a patch memory (23) is substituted for data in a read only memory (9) by applying high order addresses to a standard programmable logic array (19) having word lines (50a-50p, Figure 3). The address signals are separately applied to EXCLUSIVE OR circuits (27a-27g). The programmable logic array (19) is personalized to activate a line (21) at addresses to be substituted, and to provide logical zeros to the EXCLUSIVE OR circuits (27a-27g) which change during the patch. Only one word line is required for each continuous patch, which will vary in size on a patch-by-patch basis.