公开(公告)号：DE69705443T2

公开(公告)日：2002-05-16

申请号：DE69705443

申请日：1997-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

公开(公告)号：DE69705443D1

公开(公告)日：2001-08-09

申请号：DE69705443

申请日：1997-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

公开(公告)号：EP0814507A1

公开(公告)日：1997-12-29

申请号：EP97304339

申请日：1997-06-20

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: Method for forming three-dimensional device structures such as a trench capacitor DRAM cell comprising a second device (370) formed over a first device (315) is disclosed. A layer (350,355) having a single crystalline top surface (350) is formed above the first device (315) to provide the base for forming the active area of the second device.

Abstract translation: 公开了一种用于形成三维器件结构的方法，例如包括形成在第一器件（315）上的第二器件（370）的沟槽电容器DRAM单元。 具有单晶顶表面（350）的层（350,355）形成在第一装置（315）上方，以提供用于形成第二装置的有效区域的基座。

公开(公告)号：JPH1074907A

公开(公告)日：1998-03-17

申请号：JP16576497

申请日：1997-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased.

公开(公告)号：JPH11145415A

公开(公告)日：1999-05-28

申请号：JP24707098

申请日：1998-09-01

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  SHORT ALVIN P ,  STENGL REINHARD J ,  HO HERBERT L ,  POSCHENRIEDER BERNHARD ,  SRINIVASAN RADHIKA

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a second device of a transistor, for example, on first device of a trench, for example, in the manufacture of a dynamic random access memory using a three-dimensional trench capacitor. SOLUTION: A layer having an uppermost face of a single crystal is formed on a first device, and a layer 2 is used as a base for forming an active region of a second device. In this case, a substrate 305 having a single-crystal structure and the flat substrate surface is prepared, and a trench capacitor 315 is manufacture in the substrate. A polysilicon layer in the capacitor 315 is bored in the part lower than the substrate surface to form a recessed part, and an intermediate layer is formed in the recessed part to a height larger than the surface of a pad. This intermediate layer has the uppermost face of the single crystal. The surface of the intermediate layer and the pad are planarized in such a way that the uppermost surface of the intermediate layer substantially becomes flat to the substrate surface and a transistor 370 is manufactured on the uppermost face of the single crystal.

公开(公告)号：SG64968A1

公开(公告)日：1999-05-25

申请号：SG1997000351

申请日：1997-02-17

Applicant: SIEMENS AG ,  IBM

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10 ,  H01L21/82 ,  H01L21/70

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.