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    MANUFACTURE OF DYNAMIC RANDOM ACCESS MEMORY USING THREE-DIMENSIONAL TRENCH CAPACITOR
    1.
    发明专利
    MANUFACTURE OF DYNAMIC RANDOM ACCESS MEMORY USING THREE-DIMENSIONAL TRENCH CAPACITOR 失效

    公开(公告)号：JPH11145415A

    公开(公告)日：1999-05-28

    申请号：JP24707098

    申请日：1998-09-01

    Applicant: SIEMENS AG ,  IBM

    Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  SHORT ALVIN P ,  STENGL REINHARD J ,  HO HERBERT L ,  POSCHENRIEDER BERNHARD ,  SRINIVASAN RADHIKA

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a second device of a transistor, for example, on first device of a trench, for example, in the manufacture of a dynamic random access memory using a three-dimensional trench capacitor. SOLUTION: A layer having an uppermost face of a single crystal is formed on a first device, and a layer 2 is used as a base for forming an active region of a second device. In this case, a substrate 305 having a single-crystal structure and the flat substrate surface is prepared, and a trench capacitor 315 is manufacture in the substrate. A polysilicon layer in the capacitor 315 is bored in the part lower than the substrate surface to form a recessed part, and an intermediate layer is formed in the recessed part to a height larger than the surface of a pad. This intermediate layer has the uppermost face of the single crystal. The surface of the intermediate layer and the pad are planarized in such a way that the uppermost surface of the intermediate layer substantially becomes flat to the substrate surface and a transistor 370 is manufactured on the uppermost face of the single crystal.

    METHOD OF FACILITATING THREE-DIMENSIONAL DEVICE LAYOUT
    2.
    发明专利
    METHOD OF FACILITATING THREE-DIMENSIONAL DEVICE LAYOUT 失效

    公开(公告)号：JPH1074907A

    公开(公告)日：1998-03-17

    申请号：JP16576497

    申请日：1997-06-23

    Applicant: SIEMENS AG ,  IBM

    Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

    IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased.

    METHOD FOR MANUFACTURING SUB-GR GATE
    5.
    发明专利
    METHOD FOR MANUFACTURING SUB-GR GATE 失效

    公开(公告)号：JPH1074904A

    公开(公告)日：1998-03-17

    申请号：JP15464097

    申请日：1997-06-12

    Applicant: SIEMENS AG

    Inventor： ALSMEIER JOHANN ,  DEHM CHRISTINE ,  HAMMERL ERWIN ,  STENGL REINHARD J

    IPC: H01L29/41 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a technique far forming a sub-GR gate conductor and a mutual connection conductor line at a deep trench DRAM cell by realizing decoupling of channel doping and joint part doping which have not been attained. SOLUTION: On a semiconductor substrate, multiple layers including a sacrifice spacer, a liner, a masking layer and a resist layer are deposited, removed, and selectively etched. In that case, the sacrifice spacer is deposited on the semiconductor substrate, and a recessed part is etched at a selected part of the sacrifice spacer. In addition, the recessed part is filled with a insulation material, so that a pillar-like structure with facing surfaces is formed, and a remaining part of the sacrifice spacer is removed. A trench is etched along each surface of the pillar-like structure of insulation substance, and the trench is filled with conductive substance for forming a pair of trench gates.

    Memory cell for dynamic random access memory (DRAM)
    6.
    发明授权
    Memory cell for dynamic random access memory (DRAM) 失效
    用于动态随机存取存储器（DRAM）的存储单元

    公开(公告)号：US6383864B2

    公开(公告)日：2002-05-07

    申请号：US94089797

    申请日：1997-09-30

    Applicant: SIEMENS AG

    Inventor： SCHELLER GERD ,  GALL MARTIN ,  STENGL REINHARD J

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864

    Abstract: A memory cell, which includes a transistor and a capacitor, for use in a DRAM uses a silicon-filled vertical trench as the capacitor and a vertical transistor superposed over the vertical trench in a silicon chip. An epitaxial layer is formed at the top of the fill in the trench to impart seed information to the primarily polysilicon silicon fill in the trench. A polysilicon layer is deposited over the top surface of the chip, is apertured over the top of the trench, and has its sidewalls oxidized. The opening is then refilled with epitaxial silicon in which there is created in operation an inversion layer that serves as the channel of the transistor, and the deposited polysilicon layer serves as the word line. Another silicon layer is deposited over the epitaxial layer to serve as the bit line. The source/drain regions of the transistor are formed at the merger of the deposited layer with the fill in the trench and the merger with the polysilicon layer that serves as the bit line.

    Abstract translation: 包括用于DRAM中的晶体管和电容器的存储单元使用填充硅的垂直沟槽作为电容器，并且在硅芯片中叠加在垂直沟槽上的垂直晶体管。 在沟槽中的填充物的顶部形成外延层，以将种子信息提供给沟槽中的主要多晶硅硅填充物。 多晶硅层沉积在芯片的顶表面上，在沟槽的顶部开孔，并且其侧壁被氧化。 然后用外延硅填充开口，其中在操作中产生用作晶体管的沟道的反转层，并且沉积的多晶硅层用作字线。 在外延层上沉积另一硅层以用作位线。 晶体管的源极/漏极区域在沉积层与沟槽中的填充物的合并形成，并且与用作位线的多晶硅层的合并形成。

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