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    2.
    发明专利
    未知

    公开(公告)号：DE1154514B

    公开(公告)日：1963-09-19

    申请号：DEI0014065

    申请日：1957-12-04

    Applicant: IBM DEUTSCHLAND

    Inventor： LOGUE JOSEPH CARL ,  GOODMAN HAROLD CLARK

    IPC: G11C7/02 ,  G11C11/06

    Abstract: 849,142. Circuits employing bi-stable magnetic elements. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 3, 1957 [Dec. 5, 1956], No. 37675/57. Class 40 (9). [Also in Group XIX] In a matrix-type digital data store, Fig. 1, bipolar output signals are fed to two push-pull connected transistors 12, 15 and thence via a transformer 22, a full-wave rectifier 25, 26 and a gated amplifier 34 to an output terminal. The gated amplifier 34 is controlled by gate pulses on a terminal 51 so that it only responds to signals from the full-wave rectifier during the read-out periods and not during read-in periods.

    5.
    发明专利
    未知

    公开(公告)号：DE1023613B

    公开(公告)日：1958-01-30

    申请号：DEI0009608

    申请日：1954-12-30

    Applicant: IBM DEUTSCHLAND

    Inventor： BRUCE GEORGE DUNCAN ,  LOGUE JOSEPH CARL

    IPC: G11C19/04 ,  H03K3/30 ,  H03K3/45 ,  H03K23/76

    Abstract: 766,852. Electronic counting-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1954 [Dec. 31, 1953], No. 37379/54. Class 106 (1). [Also in Groups XXXIX and XL (c)] In a circuit triggered and reset by pulses of one polarity, the pulses are applied to transistors 10, 11 in parallel, Fig. 1, each feeding a saturable core memory device 1 so that each is effective in turn to magnetize the core in one sense or the other. Four of these circuits may be interconnected to form a decimal counter. A positive pulse applied to the transistors 10, 11 causes one, for example 10, to conduct - and pass collector current through a driving winding 3, feedback being effective over winding 5 to cause the core 2 to pass into the saturated region. The next input pulse is ineffective on transistor 10 since any conduction would tend to drive the core further into the saturated region. The pulse is, however, operative to cause transistor 11 to conduct since the windings 4, 6 are such as to magnetize the core in the opposite sense, the process continuing until saturation is reached in that direction. Alternative output pulses are suppressed by diode 24 so that pulses of one polarity appear at terminals 22, 23. In a modification, Fig. 2 (not shown), the emitters are earthed and the input applied in the common lead of windings 5, 6. Point contact transistors 33, 34 may be used, Fig. 3, with a limiting resistor 37 capable of passing only sufficient current to maintain one in a conducting state, a diode 43 tying the emitters to earth. A negative input pulse applied over transformer 41 causes conduction to pass from one transistor to the other thereby changing the state of saturation of the core 26. Decimal counter. Three circuits 52, 53, 54 may be arranged in cascade, Fig. 4, to give a count of eight, the output pulse being fed to the base circuit of transistor 34 in stage 55, Fig. 5 (not shown) to reverse the state of core 26. The ninth pulse is only effective to restore stage 52 but the tenth pulse in triggering stage 52 is also fed out over the auxiliary winding 56 to the base circuit of transistor 33 to restore stage 55, an output pulse being fed out over diode 59. An auxiliary winding 60 is arranged to feed back a paralysing pulse over diode 62 to prevent the change-over of stage 53.

    7.
    发明专利
    未知

    公开(公告)号：DE1029874B

    公开(公告)日：1958-05-14

    申请号：DEI0012238

    申请日：1956-09-25

    Applicant: IBM DEUTSCHLAND

    Inventor： LOGUE JOSEPH CARL

    IPC: H03K3/26 ,  H03K3/281 ,  H03K3/286 ,  H03K17/60 ,  H03K19/082

    Abstract: 764,100. Two stable state transistor circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 15, 1954 [Dec. 18, 1953], No. 36286/54. Class 40(6) Two complementary transistors 1, 2 are arranged with the output of each connected to the input of the other to form a loop, an input signal being applied at one point and an output derived from another. A latching circuit, that is a circuit set by one input and reset by another and a circuit set and reset by a change of polarity of a single input are described. Transistors 1, 2, Fig. 1, in the off condition with both switches 17S, 18S open, bias each other into the non-conducting state. The low collector potential of transistor 2 is applied over resistor 8 to the base of transistor 2 to bias it off, the emitter being held at the potential of battery 16. Negligible collector current flows giving a high back resistance which causes a low base current in transistor 2 with a consequent low collector current and potential near that of battery 13. When switch 17S is closed, the base potential of transistor 1 is raised causing a rise in the emitter and collector currents and fall in collector potential which is fed over resistor 3 to the base of transistor 2. The emitter and collector currents of transistor 2 rise together with the collector potential and this is fed back over resistor 8 to hold the base of transistor 1 positive and complete the regenerative loop, the opening of switch 17S now being ineffective. Operation of switch 18S raises the potential of the base of transistor 2 which cuts off at the emitter, the fall in collector potential being fed to transistor 1 to cut it off. The sources 17, 19 are usually of pulse form and by making one of larger amplitude it can be made the effective one when they occur simultaneously. The type of transistor and polarity of the batteries may be reversed, Fig. 4 (not shown). Circuit set and reset by-pulses of different polarity. In the off state with negligible collector current flowing, the collector of transistor 34, Fig. 7, is near the potential of battery 46 and resistors 37, 43 are chosen so that the base of transistor 33 is below earth and since the emitter is connected to earth over the emitter-base resistance of transistor 34, transistor 33 is cut off. As the emitter current of transistor 34 is low, the collector current is held low to complete the regeneerative loop. A positive pulse from source 41 overcomes the negative bias on the base of transistor 33 causing it to conduct and hence render transistor 34 conducting to maintain transistor 33 conducting after the input pulse has ceased. In a similar manner, the circuit is reset by a negative pulse from generator 41. The type of transistor and polarity of the batteries may be reversed, Fig. 10 (not shown).

    9.
    发明专利
    未知

    公开(公告)号：DE1014164B

    公开(公告)日：1957-08-22

    申请号：DEI0010365

    申请日：1955-06-30

    Applicant: IBM DEUTSCHLAND

    Inventor： LOGUE JOSEPH CARL ,  JUN ANDREW ERNEST BRENNEMANN

    IPC: G11C11/23

    Abstract: 796,347. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 28, 1955 [July 1, 1954], No. 18624/55. Class 106 (1). [Also in Group XL (a)] In a method of storing information in the form of electric charges on a dielectric target, the electron beam inspecting, reading and laying down the charge in an elemental area is first unblanked as a sharply focused beam and defocused whilst still impinging in the area before being blanked. The focus-defocus pulse generator 101 is connected to the electron lens of the storage tube 110. Blanking pulses from generator 106 are fed by gating means 104 to the control electrode G1, the dash pulses only being permitted when a positive signal is received from the signal plate 111 of the tube. A dash deflection generator 102 is connected in parallel with the horizontal deflection portion of voltage generator 100. Sample or strobe pulses are fed to gating means 104, which also receives information and read/write control. A modification of the circuit is described (Fig. 1, not shown). It will be seen from the diagrammatic explanation of Fig. 3, that when the beam impinges on a "dot" or positively charged area A, a negative signal D30 is released, the beam is focused for part of period t 0 -t 1 , and then defocused, thereby restoring the positive charge of the area. When a " dash " or negatively charged area B is impacted by the unblanked beam, a positive signal D31 is generated and a further dash-pulse D2a is gated to unblank the focused beam for a further period D21a, the dash deflection pulse simultaneously deflecting the beam so as to irradiate the immediately adjacent areas. The secondary electrons liberated at these areas pass to the original positively-charged elemental area and render it relatively negative, thus restoring the " dash " condition of the area. Specification 657,591 is referred to.

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