中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.023 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE69807621T2

    公开(公告)日：2003-11-27

    申请号：DE69807621

    申请日：1998-06-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

    IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

    Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

    FORMATION OF COLLAR OXIDE IN TRENCH
    2.
    发明专利
    FORMATION OF COLLAR OXIDE IN TRENCH 失效

    公开(公告)号：JPH11265882A

    公开(公告)日：1999-09-28

    申请号：JP1528999

    申请日：1999-01-25

    Applicant: IBM ,  SIEMENS AG

    Inventor： NAEEM MUNIR D ,  SENDELBACH MATTHEW J ,  WANG TING-HAO

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a collar oxide in the trench of a semiconductor substrate by selectively etching a conformal oxide layer. SOLUTION: In a semiconductor substrate 1 having (1) a trench 100, (2) (i) the filler surface demarcated by filler material for partially filling the trench 100, (ii) the upper surface outside the trench 100, and (iii) part of a sidewall of the trench which is not covered by the filler material, and (3) a conformal oxide layer formed on the upper surface, the sidewall, and the filler surface, (a) the substrate 1 is brought into contact with a mixture of hydrogen-containing fluorocarbon and a source of oxygen under the reactive ion etching conditions, and then (b) the substrate 1 is brought into contact with a mixture of fluorocarbon which does not contain hydrogen and gas for dilution under the reactive ion etching conditions, and the upper surface and the filler surface are selectively overetched while most of the conformal oxide is left over on the sidewall of the trench to form a collar oxide 41.

    3.
    发明专利
    未知

    公开(公告)号：DE69807621D1

    公开(公告)日：2002-10-10

    申请号：DE69807621

    申请日：1998-06-26

    Applicant: SIEMENS AG ,  IBM

    Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

    IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

    Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

Patent Agency Ranking