公开(公告)号：DE69807621T2

公开(公告)日：2003-11-27

申请号：DE69807621

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：JPH1174241A

公开(公告)日：1999-03-16

申请号：JP18232498

申请日：1998-06-29

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  WOLFGANG BERGNER ,  FIEGL BERNHARD ,  GEORGE R GOSSE ,  PARRIES PAUL ,  MATTHEW J SENDERBACH ,  TEIN-HAO WAN ,  WILLIAM C WILL ,  JUERGEN WITTMANN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To prevent damages to a substrate under a pad nitride layer, induced by CMP, by disposing the pad nitride layer under a conformally vapor-deposited dielectric layer and partly etching a first region on the dielectric layer disposed under a conformally vapor-deposited polysilicon layer, for removing the polysilicon layer. SOLUTION: A pad nitride layer 118 is evaporated onto a silicon mesa 114, and a TEOS layer (dielectric layer) 126 is evaporated conformally onto the pad nitride layer 118 and a silicon substrate 112. In addition, a polysilicon layer 130 is conformally evaporated onto the TEOS 126. Then, chemical and mechanical polishing(CMP) is used to planarize the polysilicon layer 130 downward to the surface of the TEOS layer 126, and a first region on the TEOS layer 126 disposed on the pad nitride 118 is thereby exposed. Further, the first region on the TEOS layer 126 is partly etched, using a first etching parameter, and thereafter the polysilicon layer 130 is removed.

公开(公告)号：JPH1126595A

公开(公告)日：1999-01-29

申请号：JP11649898

申请日：1998-04-27

Applicant: IBM ,  SIEMENS AG

Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To make shallow trench separation by a method wherein a conformal silicon oxide layer on a mesa is partially etched by selective RIE and then the silicon oxide layer is transformed to a flat silicon oxide layer using a silicon nitride pad as an etch stopper and then a conformal blanket silicon oxide layer is polished chemically and mechanically. SOLUTION: An RIE etchant is introduced from openings 48A, 48B, 48C into etching openings 50A, 50B, 50C formed inside through a gate insulating layer 44 extended through a tungsten silicide layer 42 and a doped polysilicon layer 40. Then, the surfaces of gate oxide layer segments 38/38' are exposed with a gate conductor stack 51 having source/drain windows on both sides of an N well 34 and having a dummy window wherein a P well is exposed for the later ion implantation being left over. After that, the entire surface is covered by the silicon nitride gate insulating layer 44 and then the insulating layer 44 is polished chemically and mechanically.

公开(公告)号：JPH10294362A

公开(公告)日：1998-11-04

申请号：JP9896898

申请日：1998-04-10

Applicant: IBM ,  SIEMENS AG

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To enable a process through which a shallow trench is filled in to be enhanced in manufacturing properties and yield by a method wherein an intermediate plane layer is formed, and the lower layer of a thick oxide is selectively etched to deteriorate in planarity. SOLUTION: An upper planar surface is formed so as to be flush with the fill-in upper surface 115 of a fill-in layer 110. A polish stop layer 130 is removed by the use of etching chemicals which are capable of etching both the polish stop layer 130 and a temporary fill-in layer 120, and an intermediate plane surface is kept unremoved leaving the cover part of the temporary fill-in layer 120 unremoved. A part of the fill-in layer 110 located outside the cover part of the temporary fill-in layer 120 is etched as deep as a point shallower than a trench by the use of chemicals which etch the fill-in layer 110 preferentially so as to enable the fill-in upper surface 115 of the fill-in layer 110 located above a reference surface to be flush with the fill-in upper surface 115 of the fill-in layer 110 located in the trench, whereby a planar surface is deteriorated in flatness.

公开(公告)号：DE69824481T2

公开(公告)日：2005-07-07

申请号：DE69824481

申请日：1998-04-23

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

公开(公告)号：DE69802607T2

公开(公告)日：2002-07-25

申请号：DE69802607

申请日：1998-03-12

Applicant: SIEMENS AG ,  IBM

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

公开(公告)号：DE69824481D1

公开(公告)日：2004-07-22

申请号：DE69824481

申请日：1998-04-23

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: FET devices (10) are manufactured using STI on a semiconductor substrate (11) coated with a pad (14) from which are formed raised active silicon device areas and dummy active silicon mesas (12) capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide (22) layer is deposited on the device (10) with conformal projections above the mesas (12). Then a polysilicon film (24) on the blanket silicon oxide layer (22) is deposited with conformal projections above the mesas (12). The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer (22) is exposed over the pad structures (14). Selective RIE partial etching of the conformal silicon oxide layer (22) over the mesas (12) is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer (22) which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride (14) as an etch stop.

公开(公告)号：DE69807621D1

公开(公告)日：2002-10-10

申请号：DE69807621

申请日：1998-06-26

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：DE69802607D1

公开(公告)日：2002-01-10

申请号：DE69802607

申请日：1998-03-12

Applicant: SIEMENS AG ,  IBM

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762