公开(公告)号：WO0137325A9

公开(公告)日：2002-07-04

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8, 20 - 80sccm of CO, 2 - 30sccm of O2 and 50 - 400sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2 - 30sccm的C4F8，20 - 80sccm的CO，2 - 30sccm的O2和50 - 400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：WO0137325A2

公开(公告)日：2001-05-25

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8 2

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O> 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。