CABLE BOOTS AND DUST COVER FOR RELEASING EMI SHIELDING STRAIN

    公开(公告)号:JP2001230025A

    公开(公告)日:2001-08-24

    申请号:JP2001034448

    申请日:2001-02-09

    Abstract: PROBLEM TO BE SOLVED: To provide a boot for releasing an EMI shielding strain to reduce EMI released from a receptacle of electronic equipment. SOLUTION: A flexible elongated boot body is provide with a proximal end, a distal end and an inner face 40. The inner face regulates a bore arranged at a certain measurement so as to contain an end portion of a transmission cable 14 and an associated cable connector 16, and an EMI shield is formed to extend almost over the whole length of the boot body and to shield the bore area from interfering electromagnetic radiation, whereby the distal end of the boot body is covered with the cable connector 16 and fits at least a part of a plug-in transceiver connector 18 so as to be able to surround it.

    EXPANSION PARTIAL RESPONSE MAXIMUM LIKELIHOOD METHOD (EPRML)-CHANNEL-DEVICE

    公开(公告)号:JP2001053623A

    公开(公告)日:2001-02-23

    申请号:JP2000199374

    申请日:2000-06-30

    Abstract: PROBLEM TO BE SOLVED: To obtain an expansion partial response maximum likelihood method (EPRML)-channel-device capable of making a code as efficient as possible by using a specific trellis code having three-byte error error propagation on the basis of an EPRML minimum distance channel-error. SOLUTION: An encoder decoder 12 receives an input signal and performs implement execution and realization of rate information ratio 24/26-trellis trellis code having 3-byte error error propagation on the basis of an EPRML minimum distance channel-error. A precoder 14 performs precoding processing onto a coded signal from the coder 12. An expansion partial response(EPR) channel 16 is constructed so as to receive an output from the precoder 14, and a detector 18 detects an output of the channel 16. A decoder 20 is constructed so as to apply inverse processing or inverse operation to the coder 12.

    VERTICAL SIDEWALL DEVICE ALIGNED TO CRYSTAL AXIS AND MANUFACTURE THEREOF

    公开(公告)号:JP2001044390A

    公开(公告)日:2001-02-16

    申请号:JP2000209997

    申请日:2000-07-11

    Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

    MANUFACTURE OF TRENCH DRAM CAPACITOR EMBEDDED PLATE

    公开(公告)号:JP2001044384A

    公开(公告)日:2001-02-16

    申请号:JP2000220682

    申请日:2000-07-21

    Abstract: PROBLEM TO BE SOLVED: To reduce a method for forming an embedded plate diffusion region in a deep trench storage capacitor by filling a non-photosensitive underfill material into the lower region of a trench before forming a collar at the upper region of the trench. SOLUTION: A trench 10 is covered with a thin barrier film 30, and a non- photosensitive underfill 16 is filled into the lower region of the trench 10. Then, the barrier film 30 is eliminated by an upper region 223 of the trench 10 by chemical etching using wet solution or the like. Also, the underfill 16 masks a lower region, 24 while the barrier film 30 at the upper region 22 is being removed. Then, the underfill 16 is removed from a lower region by stripping or the like by a chemical containing HF, and a collar 32 is formed at the upper region 22 by thermal oxidation growth or the like by the local oxidation process.

    SEMICONDUCTOR MEMORY CHIP
    9.
    发明专利

    公开(公告)号:JP2001014891A

    公开(公告)日:2001-01-19

    申请号:JP2000145101

    申请日:2000-05-17

    Inventor: FRANKOWSKY GERD

    Abstract: PROBLEM TO BE SOLVED: To enable testing at higher speed and more efficiently by providing a first memory array to be tested and a pattern generator formed on a memory chip, and providing a programmable memory array and a means specifying an address of pattern data stored in the programmable memory array in the pattern generator. SOLUTION: A semiconductor memory chip 100 has a memory array 102 consisting of plural memory banks 104 including a memory cell 106. A pattern generator 108 supplies a test pattern for testing the memory cell 106. A memory 14 of the pattern generator 108 can be directly accessed by data input and program-in. Pattern data is stored in the memory 114 by data input. Writing data in the memory 114 from the program and operation of overwriting can be programmed. The prescribed pattern is inputted to the pattern generator 108 by a pattern address line and programming can be performed.

    SEMICONDUCTOR MEMORY CHIP AND DRAM MEMORY CHIP

    公开(公告)号:JP2001006394A

    公开(公告)日:2001-01-12

    申请号:JP2000145244

    申请日:2000-05-17

    Inventor: FRANKOWSKY GERD

    Abstract: PROBLEM TO BE SOLVED: To reduce the testing cost of a memory cell by comparing reference data from a pattern generator with stored data from a memory cell array, and storing and outputting a first state when the stored data match the reference data, and storing and outputting a second state otherwise. SOLUTION: In a semiconductor memory device 100, reference data is supplied to a memory array and a comparator 110 from a pattern generator 112 through a read/write data line RWD to test a memory. The comparator 110 compares reference data with array data, and accumulates all compares results in an internal latch. Thereby, as a channel used for comparing normal array data with the reference data can be used, a tester can test more semiconductor memory devices in parallel, and throughput for an acceptance test is improved.

Patent Agency Ranking