公开(公告)号：WO2007002420A8

公开(公告)日：2007-03-29

申请号：PCT/US2006024507

申请日：2006-06-22

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G11C7/20

CPC classification number: G11C11/4072 ,  G11C7/20 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A memory device may (44, 46) determine its device ID in response to the order of a received training pattern. The training pattern may be transmitted over swizzled signal lines to multiple memory devices (44, 46) arranged in a logical stack. Each memory device may be packaged on a substrate (48, 50) having the swizzled signal lines. The memory devices may be physically stacked or planar. Other embodiments are described and claimed.

Abstract translation: 存储设备可以（44,46）响应于接收到的训练模式的顺序来确定其设备ID。 训练模式可以通过混杂的信号线传输到布置在逻辑堆栈中的多个存储器设备（44,46）。 每个存储器件可以封装在具有混合信号线的衬底（48,50）上。 存储器设备可以是物理堆叠的或平面的。 描述并要求保护其他实施例。

公开(公告)号：WO2006057963A3

公开(公告)日：2006-07-20

申请号：PCT/US2005042153

申请日：2005-11-17

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G06F13/28 ,  G11C29/52

CPC classification number: G11C5/04 ,  G11C7/1006 ,  G11C7/1027

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not.This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

Abstract translation: 用于存储器系统和存储器模块的方法和装置包括在实施例中。 在示例性系统中，纠错编码（ECC）数据在突发模式传输中与相同数据总线上的用户数据时间复用，使得不需要分离的芯片和数据线来支持ECC。 模块上的存储器设备每个包含与设备的可寻址段相关联的额外的间接可寻址ECC段。 时间复用的ECC数据从与突发模式传输中发送的可寻址数据相关联的间接可寻址的段中读取和写入。 在一些实施例中，支持两种类型的突发模式，一种包括ECC数据，另一种不包含ECC数据。这允许一种类型的存储器模块支持ECC和非ECC系统，并且在一些情况下使用ECC来处理某些数据 而不是用于同一系统中的其他数据。 描述并要求保护其他实施例。

公开(公告)号：WO2007002546A3

公开(公告)日：2007-06-21

申请号：PCT/US2006024720

申请日：2006-06-22

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G06F13/16

CPC classification number: G06F13/1605

Abstract: A memory agent schedules local and pass-through responses according to an identifier for each response. A response file may be large enough to store responses for a maximum number of requests that may be outstanding on a memory channel. A request file may be large enough to store requests for a maximum number of requests that may be outstanding on the memory channel. The identifier for each request and/or response may be received on the same channel link as the request and/or response. Other embodiments are described and claimed.

Abstract translation: 内存代理根据每个响应的标识符调度本地和传递响应。 响应文件可能足够大，可以存储对内存通道上未完成的最大请求数的响应。 请求文件可能足够大，以存储请求，以便在内存通道上发出最大数量的请求。 每个请求和/或响应的标识符可以在与请求和/或响应相同的信道链路上接收。 描述并要求保护其他实施例。

公开(公告)号：WO2004109526A2

公开(公告)日：2004-12-16

申请号：PCT/US2004016116

申请日：2004-05-20

Applicant: INTEL CORP

Inventor： VOGT PETE ,  MORROW WARREN ,  BRZEZINSKI DENNIS

IPC: G06F13/16 ,  G06F13/00

CPC classification number: G06F12/00 ,  G06F13/4243 ,  G06F13/4256 ,  Y02D10/14 ,  Y02D10/151

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract translation: 使用多个位通道的存储装置和方法可以重定向在位通道上的一个或多个信号。 存储器可以包括具有多个位通道的重新驱动电路，存储器件或接口以及耦合在多个位通道和存储器件或接口之间的故障切换电路。

公开(公告)号：WO2005050599A3

公开(公告)日：2006-04-20

申请号：PCT/US2004036964

申请日：2004-11-05

Applicant: INTEL CORP ,  HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

Inventor： HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

IPC: G06F13/16

CPC classification number: G06F13/16

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

Abstract translation: 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。 缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作 。 例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。 描述和要求保护其他实施例。

公开(公告)号：WO2005050448A3

公开(公告)日：2005-07-28

申请号：PCT/US2004036966

申请日：2004-11-05

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1004

Abstract: Memory apparatus and methods transmit and receive a CRC code for a first portion of a frame before the second portion of the frame is finished being transferred. The CRC may be used to check the first portion of the frame before the second portion of the frame is completely received. A command or other information in the first portion of the frame may be used without waiting for the rest of the frame. Other embodiments are described and claimed.

Abstract translation: 存储器装置和方法在帧的第二部分完成传送之前传送并接收帧的第一部分的CRC码。 CRC可用于在帧的第二部分被完全接收之前检查帧的第一部分。 可以使用帧的第一部分中的命令或其他信息而不用等待帧的其余部分。 描述并要求保护其他实施例。

公开(公告)号：WO2005050465A2

公开(公告)日：2005-06-02

申请号：PCT/US2004036835

申请日：2004-11-05

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G06F13/42 ,  G11C29/00

CPC classification number: G06F13/4256

Abstract: Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be analyzed to identify failed lanes. Other embodiments are described and claimed.

Abstract translation: 存储装置和方法选择性地将第一车道映射到第二车道。 记忆代理可以使用不同的通道映射来传送训练和返回序列。 可以分析返回序列以识别失败的车道。 描述和要求保护其他实施例。

公开(公告)号：WO2006105525A3

公开(公告)日：2007-05-18

申请号：PCT/US2006012599

申请日：2006-03-31

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  H04L1/0041 ,  H04L1/0061

Abstract: An apparatus includes a source for a command and an associated data. An error code generator generates an error code for the combined command and associated data, which is distributed among the command and the associated data. A transmitter then transmits the command and the associated data separately.

Abstract translation: 一种装置包括用于命令的源和相关联的数据。 错误代码生成器为组合命令和关联数据生成错误代码，该错误代码分布在命令和关联数据之间。 然后发射机分别发送命令和相关数据。

公开(公告)号：WO2006072107A3

公开(公告)日：2006-09-28

申请号：PCT/US2005047689

申请日：2005-12-29

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3114 ,  H01L21/4839 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/4985 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments an apparatus may comprise a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate attached to the polymer resin such that the thermally conductive substrate can spread heat from the semiconductor die.

Abstract translation: 在一些实施例中，设备可以包括半导体管芯，附接到管芯的弹性体层，连接到弹性体的带引线，通过弹性体暴露的带状引线的与管芯连接的部分，附着到带的聚合物树脂 引线和连接到聚合物树脂的导热基板，使得导热基板可以从半导体管芯散热。

公开(公告)号：WO2005050941A3

公开(公告)日：2005-07-21

申请号：PCT/US2004037285

申请日：2004-11-05

Applicant: INTEL CORP ,  VOGT PETE

Inventor： VOGT PETE

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4243 ,  G06F11/1004

Abstract: Memory apparatus and methods accumulate data between a data path and a memory device. A memory agent may have a data accumulator between a redrive circuit and a memory device or interface. The data accumulator may accumulate data to or from the redrive circuit. Other embodiments are described and claimed.

Abstract translation: 存储装置和方法在数据路径和存储设备之间累积数据。 存储器代理可以在重驱动电路和存储设备或接口之间具有数据累加器。 数据累加器可以将数据累加到重驱电路或从重驱电路累积数据。 描述并要求保护其他实施例。