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    STAIR-STACKED DICE DEVICE IN SYSTEM IN PACKAGE, AND METHODS OF MAKING SAME
    2.
    发明申请
    STAIR-STACKED DICE DEVICE IN SYSTEM IN PACKAGE, AND METHODS OF MAKING SAME 审中-公开
    包装系统中的阶梯堆叠式骰子装置及其制造方法

    公开(公告)号：WO2018058548A1

    公开(公告)日：2018-04-05

    申请号：PCT/CN2016/101130

    申请日：2016-09-30

    Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

    Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

    IPC: H01L25/00

    Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

    Abstract translation: 封装中的系统包括相对于处理器裸片垂直堆叠的阶梯式堆叠式存储器模块。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯式堆叠的存储器模块和至少一部分处理器裸片。

    INTERCONNECT STRUCTURE FABRICATED USING LITHOGRAPHIC AND DEPOSITION PROCESSES
    3.
    发明申请
    INTERCONNECT STRUCTURE FABRICATED USING LITHOGRAPHIC AND DEPOSITION PROCESSES 审中-公开

    公开(公告)号：WO2020118558A1

    公开(公告)日：2020-06-18

    申请号：PCT/CN2018/120572

    申请日：2018-12-12

    Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  XU, Zhijun

    Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  XU, Zhijun

    IPC: H01L23/525

    Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

    WEARABLE PERSONAL COMPUTER AND HEALTHCARE DEVICES
    5.
    发明申请
    WEARABLE PERSONAL COMPUTER AND HEALTHCARE DEVICES 审中-公开
    个人电脑及健康设备

    公开(公告)号：WO2016082144A1

    公开(公告)日：2016-06-02

    申请号：PCT/CN2014/092345

    申请日：2014-11-27

    Applicant: INTEL CORPORATION

    Inventor： GUO, Mao ,  ZHAO, Junfeng ,  SKINNER, Michael P. ,  XIAO, Ke ,  TANG, Jiamiao ,  LIU, Bin ,  DENG, Li

    IPC: G08B1/00

    CPC classification number: A61B5/746 ,  A61B5/0022 ,  A61B5/0816 ,  A61B5/1072 ,  A61B5/1118 ,  A61B5/4815 ,  A61B5/486 ,  A61B5/6804 ,  A61B5/6823 ,  A61B5/6831 ,  A61B5/7405 ,  A61B5/7455 ,  A61B7/00 ,  A61B2562/0219 ,  A61B2562/0247 ,  A61B2562/04 ,  A61B2562/063 ,  A61B2562/166 ,  G08B3/10 ,  G08B5/224 ,  G08B6/00 ,  G08B21/0269 ,  G08B21/0277 ,  G08B21/0283 ,  H04Q9/00 ,  H04Q2209/43

    Abstract: Embodiments described herein may fully integrate personal computing and health care into a wearable waistband having a length sensor, a pressure sensor, and a motion sensor; or into a wearable "mesh" having an array of sound sensors, which will create convenient and seamless access to a personal computer and biofeedback of the wearer. Such biofeedback from the waistband may include determining respiration rate, waist length, food quantity of a meal, sitting or sleep time, and frequency of visits to the bathroom. Such biofeedback from the mesh or array may include determining whether there is or has been damage or other issues of the heart, lungs, bones, joints, jaw, throat, arteries, digestive tract, and the like. Such biofeedback may also detect whether a person has an alergic reaction at a location, is drinking (and what volume of fluid), is walking, is jogging or is running.

    Abstract translation: 本文描述的实施例可以将个人计算和健康护理完全集成到具有长度传感器，压力传感器和运动传感器的可穿戴腰带中; 或具有声音传感器阵列的可穿戴的“网状”，其将创建便利且无缝地访问个人计算机和穿戴者的生物反馈。 来自腰带的这种生物反馈可以包括确定呼吸速率，腰围长度，膳食的食物数量，坐着或睡眠时间以及访问浴室的频率。 来自网状物或阵列的这种生物反馈可以包括确定是否存在心脏，肺，骨骼，关节，下颌，咽喉，动脉，消化道等的损伤或其它问题。 这样的生物反馈还可以检测一个人是否在某个地点发生过敏反应，正在饮酒（以及什么体积的流体）走路，正在慢跑或正在运行。

    ORGANIC SPACER FOR INTEGRATED CIRCUITS
    6.
    发明申请
    ORGANIC SPACER FOR INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：WO2021232224A1

    公开(公告)日：2021-11-25

    申请号：PCT/CN2020/090999

    申请日：2020-05-19

    Applicant: INTEL CORPORATION ,  LIU, Bin ,  YI, Fen

    Inventor： LIU, Bin ,  YI, Fen

    IPC: H01L25/065

    Abstract: Organic spacers for integrated circuits are provided. Among other things, the organic spacers provide a cost-efficient and effective solution to address issues such as coefficient of thermal expansion (CTE) mismatches, dynamic warpage, and solder joint reliability (SJR).

    DIE STACK WITH REDUCED WARPAGE
    7.
    发明申请
    DIE STACK WITH REDUCED WARPAGE 审中-公开

    公开(公告)号：WO2018161347A1

    公开(公告)日：2018-09-13

    申请号：PCT/CN2017/076286

    申请日：2017-03-10

    Applicant: INTEL CORPORATION

    Inventor： SHE, Yong ,  LIU, Bin ,  DING, Zhicheng ,  TAN, Aiping

    IPC: H05K7/20

    Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

    ELECTRONIC DEVICE PACKAGE
    8.
    发明申请
    ELECTRONIC DEVICE PACKAGE 审中-公开

    公开(公告)号：WO2018125254A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2016/069644

    申请日：2016-12-31

    Applicant: INTEL CORPORATION

    Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  KIM, Hyoung Il

    IPC: H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

    INTEGRATED CIRCUIT DIE STACKS
    9.
    发明申请
    INTEGRATED CIRCUIT DIE STACKS 审中-公开

    公开(公告)号：WO2018112687A1

    公开(公告)日：2018-06-28

    申请号：PCT/CN2016/110701

    申请日：2016-12-19

    Applicant: INTEL CORPORATION ,  LIU, Bin ,  DING, Zhicheng ,  SHE, Yong ,  TAN, Aiping ,  GUO, Mao

    Inventor： LIU, Bin ,  DING, Zhicheng ,  SHE, Yong ,  TAN, Aiping ,  GUO, Mao

    IPC: H01L25/00

    Abstract: Disclosed herein are integrated circuit (IC) die stacks, as well as related apparatuses and methods. For example, in some embodiments, an IC package may include: a package substrate having a substrate conductive contact; a first die coupled to the package substrate, wherein the first die has a first face and an opposing second face, the second face of the first die is between the first face of the first die and the package substrate, and the first die has a first conductive contact at the first face of the first die; a second die coupled to the first die, wherein the second die has a second conductive contact facing the first face of the first die; and a bondwire between the first conductive contact and the substrate conductive contact, wherein the bondwire is also in electrical contact with the second conductive contact.

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