公开(公告)号：WO2016082144A1

公开(公告)日：2016-06-02

申请号：PCT/CN2014/092345

申请日：2014-11-27

Applicant: INTEL CORPORATION

Inventor： GUO, Mao ,  ZHAO, Junfeng ,  SKINNER, Michael P. ,  XIAO, Ke ,  TANG, Jiamiao ,  LIU, Bin ,  DENG, Li

IPC: G08B1/00

CPC classification number: A61B5/746 ,  A61B5/0022 ,  A61B5/0816 ,  A61B5/1072 ,  A61B5/1118 ,  A61B5/4815 ,  A61B5/486 ,  A61B5/6804 ,  A61B5/6823 ,  A61B5/6831 ,  A61B5/7405 ,  A61B5/7455 ,  A61B7/00 ,  A61B2562/0219 ,  A61B2562/0247 ,  A61B2562/04 ,  A61B2562/063 ,  A61B2562/166 ,  G08B3/10 ,  G08B5/224 ,  G08B6/00 ,  G08B21/0269 ,  G08B21/0277 ,  G08B21/0283 ,  H04Q9/00 ,  H04Q2209/43

Abstract: Embodiments described herein may fully integrate personal computing and health care into a wearable waistband having a length sensor, a pressure sensor, and a motion sensor; or into a wearable "mesh" having an array of sound sensors, which will create convenient and seamless access to a personal computer and biofeedback of the wearer. Such biofeedback from the waistband may include determining respiration rate, waist length, food quantity of a meal, sitting or sleep time, and frequency of visits to the bathroom. Such biofeedback from the mesh or array may include determining whether there is or has been damage or other issues of the heart, lungs, bones, joints, jaw, throat, arteries, digestive tract, and the like. Such biofeedback may also detect whether a person has an alergic reaction at a location, is drinking (and what volume of fluid), is walking, is jogging or is running.

Abstract translation: 本文描述的实施例可以将个人计算和健康护理完全集成到具有长度传感器，压力传感器和运动传感器的可穿戴腰带中; 或具有声音传感器阵列的可穿戴的“网状”，其将创建便利且无缝地访问个人计算机和穿戴者的生物反馈。 来自腰带的这种生物反馈可以包括确定呼吸速率，腰围长度，膳食的食物数量，坐着或睡眠时间以及访问浴室的频率。 来自网状物或阵列的这种生物反馈可以包括确定是否存在心脏，肺，骨骼，关节，下颌，咽喉，动脉，消化道等的损伤或其它问题。 这样的生物反馈还可以检测一个人是否在某个地点发生过敏反应，正在饮酒（以及什么体积的流体）走路，正在慢跑或正在运行。

公开(公告)号：WO2018112914A1

公开(公告)日：2018-06-28

申请号：PCT/CN2016/111785

申请日：2016-12-23

Applicant: INTEL CORPORATION

Inventor： DING, Zhicheng ,  SHE, Yong ,  LIU, Bin ,  TAN, Aiping ,  DENG, Li

IPC: H01L25/065 ,  H01L23/00

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

公开(公告)号：WO2018058548A1

公开(公告)日：2018-04-05

申请号：PCT/CN2016/101130

申请日：2016-09-30

Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

IPC: H01L25/00

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract translation: 封装中的系统包括相对于处理器裸片垂直堆叠的阶梯式堆叠式存储器模块。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯式堆叠的存储器模块和至少一部分处理器裸片。

公开(公告)号：WO2018119782A1

公开(公告)日：2018-07-05

申请号：PCT/CN2016/112717

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： TAN, Aiping ,  LIU, Bin ,  DENG, Li ,  SHE, Yong ,  DING, Zhicheng ,  GUO, Mao

IPC: H01L23/31 ,  H01L25/00 ,  H01L21/52

Abstract: Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.

公开(公告)号：WO2018058416A1

公开(公告)日：2018-04-05

申请号：PCT/CN2016/100760

申请日：2016-09-29

Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

IPC: H01L23/522

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract translation:

预先封装的阶梯式堆叠内存模块安装在至少有一个附加组件的电路板上。 楼梯堆叠的存储器模块包括相对于处理器裸片垂直堆叠的多个存储器裸片。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯堆叠的存储器模块和处理器裸片的至少一部分。 矩阵也可能包含至少一个附加组件。