公开(公告)号：US11621237B2

公开(公告)日：2023-04-04

申请号：US16247312

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Jonathan W. Thibado ,  Jeffory L. Smalley ,  John C. Gulick ,  Phi Thanh ,  Mohanraj Prabhugoud ,  Chong Zhao

IPC: H05K1/02 ,  H01L23/66 ,  H01L23/498 ,  H01L23/34 ,  H01B7/04 ,  G02B6/42 ,  H01B3/30 ,  H01B7/08 ,  H01L25/10 ,  H05K1/18

Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

公开(公告)号：US11449111B2

公开(公告)日：2022-09-20

申请号：US15942280

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Eric W. Buddrius ,  Ralph V. Miele ,  Mohanraj Prabhugoud ,  David Shia ,  Jeffory L. Smalley

IPC: G06F1/18 ,  H05K7/14 ,  H05K7/18 ,  H05K7/16 ,  H05K7/10

Abstract: A microprocessor loading mechanism, comprising a bolster plate surrounding an aperture, wherein the opening is to receive a microprocessor socket, one or more torsion bars coupled to the bolster plate, and a stud coupled to each of the one or more torsion bars, wherein each stud is to receive a nut to secure a microprocessor package to the microprocessor socket within the aperture and wherein each stud is secured to the bolster plate by each corresponding torsion bar.

公开(公告)号：US12248344B2

公开(公告)日：2025-03-11

申请号：US17214230

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Kristin L. Weldon ,  David Rodriguez ,  Jin Yang ,  David Shia ,  Jimmy Chuang ,  Mohanraj Prabhugoud ,  Mark Edmund Sprenger

IPC: G06F1/20 ,  H05K7/20

Abstract: Techniques for liquid cooling interfaces with rotatable connector assemblies are disclosed. In one embodiment, a collar contacts flanges on two components of a connector assembly, preventing them from separating. In another embodiment, a housing is positioned around a stem component. The stem component has a gap between a top part and a bottom part held apart by pillars, allowing water to flow to a tubing fitting connected to the housing. A retainer on top of the stem component holds the housing in place. In yet another embodiment, an internal retainer holds a housing component in place over a stem. Other embodiments are disclosed.

公开(公告)号：US20240094476A1

公开(公告)日：2024-03-21

申请号：US17949417

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Wesley B. Morgan ,  David Shia ,  Mohanraj Prabhugoud ,  Eric J. M. Moret ,  Pooya Tadayon

IPC: G02B6/38

CPC classification number: G02B6/3871 ,  G02B6/3873 ,  G02B6/3887

Abstract: Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.

公开(公告)号：US20210183846A1

公开(公告)日：2021-06-17

申请号：US17185504

申请日：2021-02-25

Applicant: Intel Corporation

Inventor： Jeffory L. Smalley ,  Thomas Holden ,  Russell J. Wunderlich ,  Farzaneh Yahyaei-Moayyed ,  Mohanraj Prabhugoud ,  Horthense Delphine Tamdem ,  Vijaya Boddu ,  Kaladhar Radhakrishnan ,  Timothy Glen Hanna ,  Krishna Bharath ,  Judy Amanor-Boadu ,  Mark A. Schmisseur ,  Srikant Nekkanty ,  Luis E. Rosales Galvan

IPC: H01L25/18 ,  H01L23/498 ,  H01R12/71

Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.

公开(公告)号：US10324112B2

公开(公告)日：2019-06-18

申请号：US15370870

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  Andrew J. Hoitink ,  Abram M. Detofsky ,  Joe F. Walczyk

IPC: G01R1/073 ,  G01B7/00 ,  G01R1/067 ,  G01R31/28

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US12176643B2

公开(公告)日：2024-12-24

申请号：US17033386

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Thomas Boyd ,  Feifei Cheng ,  Eric W. Buddrius ,  Mohanraj Prabhugoud

IPC: H01R12/91 ,  H01R12/70 ,  H01R12/71 ,  H01R12/88 ,  H05K7/10

Abstract: Embodiments disclosed herein include sockets and electronic packages with socket architectures. In an embodiment, a socket comprises a housing with a first surface and a second surface. In an embodiment, a plurality of interconnect pins pass through the housing. In an embodiment, an alignment hole is provided through the housing. In an embodiment, an alignment post extending out from the first surface of the housing is also provided.

公开(公告)号：US12133357B2

公开(公告)日：2024-10-29

申请号：US17123760

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Jin Yang ,  David Shia ,  Mohanraj Prabhugoud ,  Olaotan Elenitoba-Johnson ,  Craig Jahne ,  Phil Geng

IPC: H05K7/20

CPC classification number: H05K7/20254 ,  H05K7/20418 ,  H05K7/20509

Abstract: Examples described herein relate to a cold plate. In some examples, the cold plate includes a surface with fins and at least two channels, wherein a first channel is shaped with a first opening extending towards the surface, a second opening proximate and across a first fin attached to the surface, and a third opening from the surface and extending away from the surface. In some examples, when a fluid is provided to the first opening, the first opening directs the fluid towards the surface, the second opening directs the fluid across the first fin, and the third opening directs the fluid away from the surface. In some examples, the second opening comprises split openings around opposite sides of the first fin.

公开(公告)号：US20240027697A1

公开(公告)日：2024-01-25

申请号：US17871558

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Wesley B. Morgan ,  Mohanraj Prabhugoud ,  David Shia ,  Eric J. M. Moret ,  Pooya Tadayon ,  Tarek A. Ibrahim

IPC: G02B6/38

CPC classification number: G02B6/3897 ,  G02B6/3885 ,  G02B6/3893

Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.

公开(公告)号：US20180045759A1

公开(公告)日：2018-02-15

申请号：US15370870

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  Andrew J. Hoitink ,  Abram M. Detofsky ,  Joe F. Walczyk

IPC: G01R1/073 ,  G01B7/00 ,  G01R31/28

CPC classification number: G01R1/07328 ,  G01B7/003 ,  G01R1/06794 ,  G01R31/2891

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.