公开(公告)号：US09635762B2

公开(公告)日：2017-04-25

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Hiroshi Demachi ,  Takeshi Miyakoshi ,  Tomoshige Chikai ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Takashi Nakamura ,  Hirokazu Honda ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/02 ,  H01L23/10 ,  H05K1/18 ,  H01L23/367 ,  H05K1/02 ,  H01L25/10 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

公开(公告)号：US20160079204A1

公开(公告)日：2016-03-17

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。

公开(公告)号：US09368474B2

公开(公告)日：2016-06-14

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。