公开(公告)号：US20170005044A1

公开(公告)日：2017-01-05

申请号：US15198785

申请日：2016-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Kiminori ISHIDO ,  Michiaki TAMAKAWA ,  Toshihiro IWASAKI

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/19105

Abstract: The present invention is to provide a semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

Abstract translation: 本发明提供一种半导体器件，其中绝缘材料层不包含玻璃布或无纺布等增强纤维，并且能够使金属薄膜布线层小型化，金属通孔的直径减小， 层间厚度减小。 半导体器件包括绝缘材料层，其包括用不含增强纤维的绝缘材料密封的一个或多个半导体元件，多个金属薄膜布线层，将金属薄膜布线层电连接在一起的金属通孔和电极 半导体元件和金属薄膜布线层在一起，以及布置在绝缘材料层的一个主表面上的翘曲调节层，以抵消绝缘材料层的翘曲，以减少半导体器件的翘曲。

公开(公告)号：US20160172580A1

公开(公告)日：2016-06-16

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki MATSUBARA ,  Toshihiro IWASAKI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Shinji WATANABE ,  Michiaki TAMAKAWA

IPC: H01L43/02 ,  H01L43/08

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall with a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与所述存储元件的侧面间隔一定距离地形成为壁的软磁性材料，以便部分或全部地包围所述存储元件侧表面，所述磁屏蔽部磁性地连接到所述软磁 层。

公开(公告)号：US20150371934A1

公开(公告)日：2015-12-24

申请号：US14744946

申请日：2015-06-19

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu HONDA ,  Shinji WATANABE ,  Toshihiro IWASAKI ,  Kiminori ISHIDO ,  Koichiro NIWA ,  Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Shotaro SAKUMOTO ,  Hiroaki MATSUBARA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2224/83

Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Abstract translation: 一种半导体封装，包括布置有在后侧到达半导体器件的第一孔的支撑衬底，半导体器件通过粘合剂粘合到支撑衬底的表面，覆盖半导体器件的绝缘层和用于连接 半导体器件和通过绝缘层的外部端子。 粘合剂可以形成第一孔的一部分。 此外，可以在第一孔中布置散热部，并且可以在第一孔中填充金属材料。

公开(公告)号：US20170263560A1

公开(公告)日：2017-09-14

申请号：US15419091

申请日：2017-01-30

Applicant: J-Devices Corporation

Inventor： Hiroaki MATSUBARA ,  Tomoshige CHIKAI ,  Naoki HAYASHI ,  Toshihiro IWASAKI

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing miniaturization of signal lines and increasing film thickness. To accomplish this object, the present invention is configured as an interconnect structure including a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

公开(公告)号：US20160027715A1

公开(公告)日：2016-01-28

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji WATANABE ,  Sumikazu HOSOYAMADA ,  Shingo NAKAMURA ,  Hiroshi DEMACHI ,  Takeshi MIYAKOSHI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Hiroaki MATSUBARA ,  Takashi NAKAMURA ,  Hirokazu HONDA ,  Yoshikazu KUMAGAYA ,  Shotaro SAKUMOTO ,  Toshihiro IWASAKI ,  Michiaki TAMAKAWA

IPC: H01L23/373 ,  H05K1/18 ,  H01L23/31 ,  H05K1/02 ,  H01L25/065 ,  H01L23/367

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Abstract translation: 叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体器件; 第二半导体封装，包括第二电路板和安装在第二电路板上的第二半导体器件，第二半导体封装堆叠在第一半导体封装上; 以及设置在第一半导体器件上的传热部件和第一电路板的一部分，该部分围绕第一半导体器件。