公开(公告)号：JPH08148507A

公开(公告)日：1996-06-07

申请号：JP31538794

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KEIKOU ,  BEI INKEI ,  KATA HIROKI ,  KIN KEISHIYU

IPC: H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338

Abstract: PURPOSE: To contribute to high-density integration by reducing a gap between a gate and an ohmic electrode and by reducing a source resistance of a component. CONSTITUTION: Insulation films 104, 105 are vapor-deposited on the surface of a substrate at a first temperature (T1) and a second temperature (T2) (T1>T2), and dry etching is made selectively. Since the second insulation layer 105, which forms an upper layer, has a higher etching rate than the first insulation layer 104 which forms a lower layer, when etching of the first insulation layer 104 is completed and a portion of the substrate which corresponds to a gate is exposed, an excessive etching of the side faces of the second insulation film 105 is started to define a T-shaped space. A T-shaped gate electrode is formed using this space.

公开(公告)号：JPH06268665A

公开(公告)日：1994-09-22

申请号：JP35275593

申请日：1993-12-29

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KEISHIYU ,  KIN SHIYOUSHIYU ,  SAI FUMIMOTO

IPC: H04J3/00 ,  H04J3/24 ,  H04L12/00 ,  H04N7/24 ,  H04N7/58 ,  H04N21/2365 ,  H04N21/643 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/48

Abstract: PURPOSE: To prevent the deterioration of channel efficiency by storing an ATM cell input circuit in an input buffer by means of the signal that notifies the beginning of a cell. CONSTITUTION: An ATM cell input circuit is constructed so as to be stored in an input buffer by the signal that detects the cell synchronization with an input signal and notifies the beginning of a cell. An ATM cell input circuit part includes a header buffer and a payload buffer which store the headers and payloads separated and extracted from the cells supplied to each input, and the separated headers are analyzed for decision of the cell transmission sequence. The buffer overflow conditions are decreased by a priority encoder which processes with preference the input terminal where many cells are stored in the buffer and reduces the load of the input terminal having heavy traffic load. The header value is changed based on the decision sequence of the FIFO storage level information on every input terminal, and the cell transmission sequence is decided based on the service priority. Thus, the deterioration of channel efficiency is prevented.