公开(公告)号：MY193935A

公开(公告)日：2022-11-02

申请号：MYPI2015701758

申请日：2015-05-30

Applicant: MIMOS BERHAD

Inventor： LAM KIEN SIENG

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/42

Abstract: A method of controlling a bus access priority order in multiple masters I2C bus is provided, characterized in that, the method includes extending I2C packet by adding a priority frame before address and data packets; the method further includes the steps of initiating a transaction onto a common bus by issuing a START bit (101), setting an access priority level dynamically in a subsequent 7-bit frame (103), setting a transfer direction to WRITE (105), ignore the ACK bit (106), issue a Repeated START bit to continue holding bus access and readdressing to a designated slave (107), such that, a first master that produces a value of ?1? when other masters produce a ?0? loses arbitration to gain priority to access the bus.

公开(公告)号：MY187705A

公开(公告)日：2021-10-13

申请号：MYPI2012701200

申请日：2012-12-17

Applicant: MIMOS BERHAD

Inventor： LAM KIEN SIENG

IPC: G01R23/15 ,  G04F10/00 ,  H03L7/085

Abstract: The present invention relates to a system (100) for determining frequency of a signal, comprising: an input (10) for receiving a signal; a delaying means (20) comprising a plurality of first delay cells (21), connected to the input (10) for receiving the signal, and delaying the signal by a first predetermined period to produce delayed signals; and an evaluating means (30) comprising a plurality of capturing means (32) connected to the delaying means (20) for capturing the delay signals and determining frequency of the signal; characterized in that the evaluating means (30) further comprises: a second delay cell (31) connected to the input (10) and at least a corresponding capturing means (32) for delaying the signal by a second predetermined period; a detector (33) connected to the plurality of capturing means (32) for receiving the captured delayed signals and detecting a predetermined pattern; and a processor (34) operating with the detector (33) for determining frequency of the signal, wherein the signal is a clock signal. Most illustrative drawing: Figure 1

公开(公告)号：MY169787A

公开(公告)日：2019-05-15

申请号：MYPI2010700084

申请日：2010-11-29

Applicant: MIMOS BERHAD

Inventor： LAM KIEN SIENG ,  MOHAMAD YUSRI MOHAMAD YUSOF ,  SUHAIMI BAHISHAM JUSOH @ YUSOFF

Abstract: The present invention provides a System-on-Chip which consists of a plurality of DSPs (Digital Signal Processor) coupled with a plurality of hardware accelerators capable of providing high performance computational function and flexibility for future updates. A master processor [14] coordinates MAC and PHY layer operation and subdivides frequency and time domain operation to two secondary processors [16, 18]. An embodiment of the SoC architecture according to the present invention further includes a crypto engine, FEC (Forward-Error-Correction) engine and FFT (Fast-Fourier-Transform) engine, ADC (Analog-to-Digital converter) interface, DAC (Digital-to-Analog converter) interface, and RF (Radio-frequency) interface; a peripheral subsystem in which consist of a plurality of controllers connected through system bus; and a DSP-to-Peripheral bridge which coupled to DSP-1 and the peripheral subsystem wherein said bridge is responsible for critical protocol conversion and eliminates contention in data path.