公开(公告)号：MY183600A

公开(公告)日：2021-03-02

申请号：MYPI2011700138

申请日：2011-09-12

Applicant: MIMOS BERHAD

Inventor： MOHAMAD YUSRI MOHAMAD YUSOF ,  YASZRINA BINTI MOHAMAD YASSIN

Abstract: The present invention relates to an apparatus and method for interleaving within a communication system. The apparatus for interleaving within a communication system comprises an interleaver (100), and a memory device (200). The memory device (200) further includes M independent memory rows, wherein M is a multiple of k. The interleaver (100) further includes M address registers (120), a first switch (110), M select-swap circuit (130), a second switch (120), a couple merging circuit (150) and M-byte output registers (160). The most illustrative drawing: FIG. 2

公开(公告)号：MY174303A

公开(公告)日：2020-04-06

申请号：MYPI2011002860

申请日：2009-06-30

Applicant: MIMOS BERHAD

Inventor： SHAHIRINA MOHD TAHIR ,  MOHAMMED ABDO SAEED ,  MOHAMAD YUSRI MOHAMAD YUSOF ,  LOW SWEE LEONG ,  MOHAMAD ZARIN ABDUL AZIZ ,  AZMI YAACOB ,  WAN ZAWAWI ,  SYAIFUL HAZLI HAMDAN

Abstract: A method of producing signals to emulate TETRA direct mode physical layer to a broadband network, particularly WiMAX network is disclosed. Frames of broadband signals are arranged as a time slot to form a direct mode multiframe, said multiframe is made up of 18 direct mode frames according to TETRA direct mode specification. Two time slots are provided for a call transaction, a first and third time slot within a direct mode frame, for every communication channel. A proper modulation is later assigned for each direct mode burst including linearization burst, synchronization burst and normal burst. The preamble of direct mode burst shall be different from the one used for WiMAX.

公开(公告)号：MY172620A

公开(公告)日：2019-12-06

申请号：MYPI2014000196

申请日：2014-01-22

Applicant: MIMOS BERHAD

Inventor： YASZRINA BINTI MOHAMAD YASSIN ,  MOHAMAD YUSRI MOHAMAD YUSOF

Abstract: The embodiments herein disclose a system (1103) and method for arbitrary bit permutation. According to one embodiment a method involving log2(n) instances of bit distribution (BDST) instruction and in another embodiment involving log2(n) instances of bit separation (BSEP) instructions to perform an arbitrary bit permutation on a programmable processor (1101) is disclosed. In one instance of the embodiment, the permute instruction separates selected bits to one side in order and unselected bits to the other side in reverse order and in an another instance of the embodiment, the permute instruction distributes sequence of bits from one side to selected bit positions in order and sequence of bits from the other side to unselected bit positions in reverse order. Most illustrative diagram: Figure 1

公开(公告)号：MY174802A

公开(公告)日：2020-05-15

申请号：MYPI2011700109

申请日：2011-07-12

Applicant: MIMOS BERHAD

Inventor： MOHAMAD YUSRI MOHAMAD YUSOF ,  DEVI PRASAD ,  SMRUTI SANTOSH PALAI

Abstract: A method of performing bit permutation by separating marked 1-bit and marked 0-bit is disclosed. The sequence of order of 1-bit marked bits position in a lower part of register is preserved while the sequence of order of 0-bit marked bits position in an upper part of register is reversed. The bit permutation is performed by providing a delta network (801, 803) of 2x2 switches (201 or 202), preferably flip network of 2x2 switches. The delta network is performed by a parity prefix generation circuit (600). The parity prefix generation circuit is performed by a plurality of XOR operators (601, 602, 603) to generate control signals.

公开(公告)号：MY169787A

公开(公告)日：2019-05-15

申请号：MYPI2010700084

申请日：2010-11-29

Applicant: MIMOS BERHAD

Inventor： LAM KIEN SIENG ,  MOHAMAD YUSRI MOHAMAD YUSOF ,  SUHAIMI BAHISHAM JUSOH @ YUSOFF

Abstract: The present invention provides a System-on-Chip which consists of a plurality of DSPs (Digital Signal Processor) coupled with a plurality of hardware accelerators capable of providing high performance computational function and flexibility for future updates. A master processor [14] coordinates MAC and PHY layer operation and subdivides frequency and time domain operation to two secondary processors [16, 18]. An embodiment of the SoC architecture according to the present invention further includes a crypto engine, FEC (Forward-Error-Correction) engine and FFT (Fast-Fourier-Transform) engine, ADC (Analog-to-Digital converter) interface, DAC (Digital-to-Analog converter) interface, and RF (Radio-frequency) interface; a peripheral subsystem in which consist of a plurality of controllers connected through system bus; and a DSP-to-Peripheral bridge which coupled to DSP-1 and the peripheral subsystem wherein said bridge is responsible for critical protocol conversion and eliminates contention in data path.