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    RAIL-TO-RAIL DELAY LINE FOR TIME ANALOG-TO-DIGITAL CONVERTERS
    2.
    发明申请
    RAIL-TO-RAIL DELAY LINE FOR TIME ANALOG-TO-DIGITAL CONVERTERS 审中-公开
    用于时间到数字转换器的轨至轨延迟线

    公开(公告)号：WO2007019288A1

    公开(公告)日：2007-02-15

    申请号：PCT/US2006/030400

    申请日：2006-08-03

    Applicant: QUALCOMM INCORPORATED ,  KESKIN, Mustafa

    Inventor： KESKIN, Mustafa

    IPC: H03M1/18 ,  H03M1/50

    CPC classification number: G04F10/005 ,  H03M1/188 ,  H03M1/502

    Abstract: A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

    Abstract translation: 时间 - 模数转换器（TAD）利用时间 - 数字方式进行模数转换。 TAD包括两个电压 - 延迟转换器（VDC），例如CMOS反相器链，以增加TAD的动态范围。 每个VDC可以处理不同范围的输入电压。 比较器将输入信号电压与对应于不同输入电压范围的参考电压进行比较，选择器根据输入信号所在的范围选择一个VDC线路输出。 滤波器根据来自所选输出的延迟信号估计输入信号电压。

    DYNAMIC AND FAST LOCAL HOTSPOT SEARCH AND REAL TIME TEMPERATURE MONITORING
    4.
    发明申请
    DYNAMIC AND FAST LOCAL HOTSPOT SEARCH AND REAL TIME TEMPERATURE MONITORING 审中-公开
    动态快速局部热靴搜索和实时温度监测

    公开(公告)号：WO2018049309A1

    公开(公告)日：2018-03-15

    申请号：PCT/US2017/050920

    申请日：2017-09-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： KESKIN, Mustafa ,  ROHAM, Masoud ,  SAEIDI, Mehdi ,  DERBYSHIRE, Amy ,  GILMORE, Robert ,  CHUA-EOAN, Lew

    IPC: G06F1/20

    CPC classification number: G01K1/026 ,  G01K1/14 ,  G05D23/1917 ,  G06F1/206 ,  G06F12/1009 ,  G06F2212/1016 ,  Y02D10/16

    Abstract: In certain aspects, a method for temperature monitoring comprises receiving temperature readings from a plurality of temperature sensors on a chip, and determining an average or a sum of the temperature readings from the temperature sensors. The sum may be a weighted sum of the temperature readings. The method also comprises computing a temperature at a location on the chip based on the average or sum of the temperature readings. The location may be located at approximately a centroid of the locations of the temperature sensors, an estimated hotspot location on the chip, or another location on the chip.

    Abstract translation: 在某些方面，用于温度监测的方法包括接收来自芯片上的多个温度传感器的温度读数，并且确定来自温度传感器的温度读数的平均值或总和。 总和可以是温度读数的加权和。 该方法还包括基于温度读数的平均值或总和来计算芯片上的位置处的温度。 位置可以位于温度传感器的位置，芯片上估计的热点位置或芯片上的另一位置的大致中心处。

    DELAY CIRCUITS MATCHING DELAYS OF SYNCHRONOUS CIRCUITS
    6.
    发明公开
    DELAY CIRCUITS MATCHING DELAYS OF SYNCHRONOUS CIRCUITS 审中-公开
    MITVERZÖGERUNGENSYNCHRONER SCHALTUNGENÜBEREINSTIMMENDEVERZÖGERUNGSSCHALTUNGEN

    公开(公告)号：EP2212996A1

    公开(公告)日：2010-08-04

    申请号：EP08833259.8

    申请日：2008-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： KESKIN, Mustafa ,  PEDRALI-NOY, Marzio

    IPC: H03K3/037

    CPC classification number: H03K3/037

    Abstract: Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.

    Abstract translation: 描述了能够提供紧密匹配同步电路的传播延迟的延迟的延迟电路。 在一种设计中，装置包括同步电路和延迟电路。 同步电路包括从数据输入到数据输出的前向路径。 同步电路接收输入数据并提供具有传播延迟的输出数据。 延迟电路接收输入信号并提供具有与同步电路的传播延迟匹配的延迟的延迟输入信号。 延迟电路在同步电路的正向通路中包括至少两个逻辑门。 同步和延迟电路可以基于相同或类似的电路架构来实现。 延迟电路可以基于同步电路的副本，其中复制品具有反馈回路断开，并且时钟输入耦合到适当的逻辑值以总是使能延迟电路。

    PARAMETERIZED ACTIVATION FUNCTIONS TO ADJUST MODEL LINEARITY
    7.
    发明申请
    PARAMETERIZED ACTIVATION FUNCTIONS TO ADJUST MODEL LINEARITY 审中-公开

    公开(公告)号：WO2023023605A1

    公开(公告)日：2023-02-23

    申请号：PCT/US2022/075154

    申请日：2022-08-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： LIN, Jamie, Menjay ,  PORIKLI, Fatih, Murat ,  KESKIN, Mustafa

    IPC: G06N3/04 ,  G06N3/08

    Abstract: Certain aspects of the present disclosure provide techniques for parameterized activation functions. Input data is processed with at least one layer of the neural network model comprising a parameterized activation function, and at least one trainable parameter of the parameterized activation function is updated based at least in part on output from the at least one layer of the neural network model. The at least one trainable parameter may adjust at least one of a range over which the parameterized activation function is nonlinear or a shape of the parameterized activation function, and/or may adjust a location of at least one pivot of the parameterized activation function.

    FASTER BATTERY CHARGING IN CONSUMER ELECTRONIC DEVICES
    8.
    发明申请
    FASTER BATTERY CHARGING IN CONSUMER ELECTRONIC DEVICES 审中-公开
    消费电子设备中更快的电池充电

    公开(公告)号：WO2016118290A1

    公开(公告)日：2016-07-28

    申请号：PCT/US2015/067682

    申请日：2015-12-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： KESKIN, Mustafa ,  AHMAD-ASSI, Hani ,  SHEEHY, Paul Brian ,  GILMORE, Robert Philip

    IPC: H02J7/00

    CPC classification number: H02J7/0057 ,  H02J7/0055 ,  H02J7/0068 ,  H02J7/007 ,  H02J2007/0062 ,  H02J2007/0095

    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus detects a level of power received from each of a plurality of sources. The apparatus directs the power received from a first source to a charging circuit and directs the power received from at least a second source to the charging circuit. The apparatus directs the power received from the first source to the charging circuit by comparing the detected level of the power with a threshold and directing the power to the charging circuit based on a result of the comparison. The apparatus directs the power received from the at least a second source to the charging circuit by comparing the detected level of the power with the threshold and directing the power to the charging circuit based on a result of the comparison.

    Abstract translation: 在本公开的一方面，提供了一种方法，计算机可读介质和装置。 该装置检测从多个源中的每一个接收的功率电平。 该装置将从第一源接收的功率引导到充电电路，并将从至少第二源接收的功率引导到充电电路。 该装置通过将检测到的功率电平与阈值进行比较，将从第一源接收的功率引导到充电电路，并且基于比较的结果将功率引导到充电电路。 该装置通过将检测到的功率水平与阈值进行比较，并将该功率定向到充电电路，从而将从至少第二源所接收的功率引导到充电电路。

    PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION
    9.
    发明申请
    PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION 审中-公开
    具有整数和时间分辨率的可编程延迟电路

    公开(公告)号：WO2009086018A1

    公开(公告)日：2009-07-09

    申请号：PCT/US2008/087545

    申请日：2008-12-18

    Applicant: QUALCOMM INCORPORATED ,  KESKIN, Mustafa ,  PEDRALI-NOY, Marzio

    Inventor： KESKIN, Mustafa ,  PEDRALI-NOY, Marzio

    IPC: H03K5/13

    CPC classification number: H03K5/131

    Abstract: A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.

    Abstract translation: 描述了能够提供整数和分数时间分辨率的延迟的可编程延迟电路。 在一个示例性设计中，装置包括第一和第二延迟电路。 第一延迟电路提供整数个时间单位的第一延迟。 第二延迟电路耦合到第一延迟电路并且提供一个时间单位的一小部分的第二延迟。 第一延迟电路可以包括串联耦合的多个单位延迟单元。 每个单元延迟单元可以在启用时提供一个时间单位的延迟。 第二延迟电路可以具有第一和第二路径。 当选择时，第一路径可以提供更短的延迟，并且第二路径可以在选择时提供更长的延迟。 第二路径可以耦合到至少一个虚拟逻辑门，其提供额外的负载以获得用于第二路径的更长的延迟。

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