公开(公告)号：WO2016029050A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/046161

申请日：2015-08-20

Applicant: QUALCOMM INCORPORATED

Inventor： MIRHAJ, Seyed Arash ,  WADHWA, Sameer ,  ALLADI, Dinesh Jagannath ,  YAMAMOTO, Kentaro ,  WEN, Xiaoke ,  ENSAFDARAN, Masoud ,  CHEN, Weihua

IPC: H03M1/06

CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。

公开(公告)号：WO2013067192A1

公开(公告)日：2013-05-10

申请号：PCT/US2012/063080

申请日：2012-11-01

Applicant: QUALCOMM INCORPORATED

Inventor： WADHWA, Sameer

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: A curvature-compensated band-gap voltage reference circuit includes an operational amplifier and a high-frequency gain stage coupled to an output of the operational amplifier. The circuit also includes an electronic device and a matching circuit.

Abstract translation: 曲率补偿带隙电压参考电路包括运算放大器和耦合到运算放大器的输出的高频增益级。 电路还包括电子设备和匹配电路。

公开(公告)号：WO2022192463A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/019640

申请日：2022-03-09

Applicant: QUALCOMM INCORPORATED

Inventor： MIRHAJ, Seyed Arash ,  SRIVASTAVA, Ankit ,  WADHWA, Sameer

IPC: G06F7/544

Abstract: Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

公开(公告)号：WO2019182692A1

公开(公告)日：2019-09-26

申请号：PCT/US2019/017435

申请日：2019-02-11

Applicant: QUALCOMM INCORPORATED

Inventor： WADHWA, Sameer ,  MCINTYRE, James Hendrie ,  SRIPURAM, Raghunatha Reddy ,  LIU, Kezhen

IPC: G06F3/041 ,  G06F3/044

Abstract: A touchscreen display including a touchscreen panel with a set of spaced-apart electrically-conductive transmit lines and a set of spaced-apart electrically-conductive receive lines extending in orthogonal directions. A set of class-D transmit drivers generate transmit signals applied to the transmit lines based on a driving pulse-width- modulated (PWM) signals, respectively. The PWM signals control the amplitude, phase, and slew rate of the pulses of the transmit signals, respectively. The parameters of the pulses are controlled so that the transmit signals arrive with substantially the same amplitude, phase, and slew rate at each receiver regardless of which transmit driver generated the transmit signal. This allows a single anti -phase signal at each receiver to substantially cancel out the receive signal during no panel load.

公开(公告)号：WO2022159272A1

公开(公告)日：2022-07-28

申请号：PCT/US2022/011345

申请日：2022-01-05

Applicant: QUALCOMM INCORPORATED

Inventor： MIRHAJ, Seyed Arash ,  CHEN, Xiaonan ,  SRIVASTAVA, Ankit ,  WADHWA, Sameer ,  WANG, Zhongze

IPC: G11C11/419 ,  G11C7/10 ,  G11C19/28

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

公开(公告)号：WO2019108352A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/059529

申请日：2018-11-07

Applicant: QUALCOMM INCORPORATED

Inventor： ELHEBEARY, Mahmoud Mohamed Rashad Ibrahim ,  WADHWA, Sameer

IPC: G05F1/575 ,  G05F1/577

Abstract: A wide-tuning range low output impedance flip voltage follower (FVF) low dropout regulator (LDO) for large capacitor switching loads is disclosed. In some implementations, the LDO includes an operational amplifier and a FVF. The FVF can have a gain device, a source follower device, and an adaptive level shifter coupled between a drain of the source follower device and a gate of the gain device.

公开(公告)号：WO2017048549A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/050435

申请日：2016-09-06

Applicant: QUALCOMM INCORPORATED

Inventor： WADHWA, Sameer ,  MATHE, Lennart Karl-Axel

IPC: G06K9/00

CPC classification number: A61B8/5269 ,  A61B8/14 ,  A61B8/4494 ,  G06K9/0002

Abstract: Apparatus and method for generating a DC pixel voltage are disclosed. The apparatus includes an amplifier configured to amplify an input signal to generate a voltage signal, wherein the input signal is generated in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating via a piezoelectric layer; a noise reduction circuit configured to pass the voltage signal from an output of the amplifier to a node, while reducing a propagation of noise from the output of the amplifier to the node; and a circuit configured to generate a DC pixel voltage based on the reduced- noise voltage signal.

Abstract translation: 公开了用于产生DC像素电压的装置和方法。 所述装置包括：放大器，被配置为放大输入信号以产生电压信号，其中所述输入信号是响应于经由压电层反射待成像和传播的超声波产生的; 噪声降低电路，被配置为将电压信号从放大器的输出传递到节点，同时减少噪声从放大器的输出到节点的传播; 以及电路，被配置为基于所述降低噪声电压信号产生DC像素电压。

公开(公告)号：WO2017040018A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/047103

申请日：2016-08-15

Applicant: QUALCOMM INCORPORATED

Inventor： MATHE, Lennart Karl-Axel ,  WADHWA, Sameer ,  XIA, Lingli

IPC: G01S7/52 ,  G06K9/00 ,  G01S15/89

CPC classification number: A61B5/117 ,  G01S7/52079 ,  G01S15/8906 ,  G06K9/0002 ,  H01L27/20 ,  H03K17/975

Abstract: An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.

Abstract translation: 公开了一种诸如用于超声波成像装置的像素传感器的装置。 该装置包括耦合到压电层的第一金属化层，其中在第一金属化层处响应于反射待被成像的物体（例如，用户的指纹）并传播通过的超声波形成第一电压 所述压电层，并且其中所述第一金属化层位于衬底上方; 位于第一金属化层和衬底之间的第二金属化层; 以及被配置为向第二金属化层施加第二电压以减小第一金属化层和衬底之间的寄生电容的器件。

公开(公告)号：WO2013022678A3

公开(公告)日：2013-02-14

申请号：PCT/US2012/049224

申请日：2012-08-01

Applicant: QUALCOMM INCORPORATED ,  RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

Inventor： RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

IPC: H03L7/24 ,  H03L7/07

Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.

公开(公告)号：WO2010068682A3

公开(公告)日：2010-06-17

申请号：PCT/US2009/067359

申请日：2009-12-09

Applicant: QUALCOMM Incorporated ,  WADHWA, Sameer

Inventor： WADHWA, Sameer

IPC: G05F1/56 ,  G05F1/575

Abstract: A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.