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    Timing control for a memory
    2.
    发明公开
    Timing control for a memory 失效
    一个记忆的时序控制

    公开(公告)号：EP0422939A3

    公开(公告)日：1991-09-04

    申请号：EP90311168.0

    申请日：1990-10-11

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

    IPC: G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/14 ,  Y10S438/926

    Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common word line (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy word line and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line is a fixed multiple of the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential on the dummy bit line (18).

    Repairable memory circuit
    4.
    发明公开
    Repairable memory circuit 失效
    Reparierbare Speicherschaltung。

    公开(公告)号：EP0434200A1

    公开(公告)日：1991-06-26

    申请号：EP90311876.8

    申请日：1990-10-30

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

    IPC: G06F11/20

    CPC classification number: G11C29/848

    Abstract: A memory circuit comprises a memory array (1) having a plurality of memory cells arranged in rows and columns;
    a plurality of column select circuits (CS₀-CS₇) for enabling access to columns in said array, each column select circuit being associated with a respective group of said columns and being arranged to access a selected one of the columns in the respective group;
    at least one spare memory column (14);
    a plurality of read/write circuits (R/W₀-R/W₇) associated respectively with the said groups, and with said spare column, for reading or writing data bits between the data bus and the columns selected by the column select circuits; and
    routing circuitry (8) connected between the read/write circuits and the data bus and being programmable with information identifying at least one faulty column, the routing circuitry being operable in response to an attempted access to said faulty column to disconnect from the data bus the read/write circuit associated with the group containing the faulty column and to connect to the data bus the read/write circuit associated with the spare column thereby to transfer data between said spare column and the data bus.

    Abstract translation: 存储器电路包括具有以行和列排列的多个存储器单元的存储器阵列（1） 多个列选择电路（CS0-CS7），用于使得能够访问所述阵列中的列，每个列选择电路与相应的所述列组相关联，并被布置成访问相应组中的所选列中的一个; 至少一个备用存储器列（14）; 分别与所述组相关联的多个读/写电路（R / W0-R / W7）和所述备用列，用于在数据总线和由列选择电路选择的列之间读取或写入数据位; 以及连接在所述读/写电路和所述数据总线之间并且可识别至少一个故障列的信息的路由电路（8），所述路由电路可响应于对所述故障列的尝试访问而与所述数据总线断开连接 与包含故障列的组相关联的读/写电路，并且与数据总线连接与备用列相关联的读/写电路，从而在所述备用列和数据总线之间传送数据。

    Timing control for a memory
    7.
    发明公开
    Timing control for a memory 失效
    Taktsteuerungfüreinen Speicher。

    公开(公告)号：EP0422939A2

    公开(公告)日：1991-04-17

    申请号：EP90311168.0

    申请日：1990-10-11

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

    IPC: G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/14 ,  Y10S438/926

    Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common word line (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy word line and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line is a fixed multiple of the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential on the dummy bit line (18).

    Abstract translation: 存储器电路包括以行和列排列的多个存储器单元（2），每行中的单元连接到公共字线（4），并且每列中的单元连接在一对位线（6， 8），当访问存储器单元以读取时，产生电压差; 以及定时电路（16），用于产生定时信号，以根据实现预定值的所述电压差来控制另外的电路。 存储电路具有连接到虚拟单元列的虚拟位线，每个虚设单元具有与存储单元相同的结构。 多个所述虚拟单元（22）具有存储在其中的位值，并且连接到虚拟字线，并且所述虚拟单元的剩余部分变为非活动状态，由此在与被访问单元格的字线同时寻址伪字线的情况下， 预定数量的虚拟单元经由虚拟位线放电，使得在虚拟位线上产生的电压是在所访问的单元的位线之间产生的电压差的固定倍数。 定时电路（16）被连接以接收虚拟位线（18）上的电压差。

    Current sensing amplifier for a memory
    8.
    发明公开
    Current sensing amplifier for a memory 失效
    Stromabfühlverstärkerfüreinen Speicher。

    公开(公告)号：EP0411818A2

    公开(公告)日：1991-02-06

    申请号：EP90308152.9

    申请日：1990-07-25

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

    IPC: G11C11/419 ,  G11C7/06

    CPC classification number: G11C11/419 ,  G11C7/065 ,  G11C2207/063

    Abstract: A current sensing amplifier has two crosscoupled input p-channel transistors, two load transistors connected respectively to the input transistors and a switch element. Output voltages are developed across the load transistors. The amplifier senses differences in currents supplied to the input transistors and drives the output voltages in opposite directions in a sense dependent on the sense of the difference of the currents.

    Abstract translation: 电流感测放大器具有两个交叉耦合的输入p沟道晶体管，两个负载晶体管分别连接到输入晶体管和开关元件。 跨负载晶体管产生输出电压。 放大器感测提供给输入晶体管的电流差异，并在某种意义上驱动输出电压在相反方向，这取决于电流差异的感觉。

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