公开(公告)号：WO1998019463A1

公开(公告)日：1998-05-07

申请号：PCT/GB1997002984

申请日：1997-10-29

Applicant: SGS-THOMSON MICROELECTRONICS LIMITED ,  COLE, Anthony, James, Carvallo

Inventor： SGS-THOMSON MICROELECTRONICS LIMITED

IPC: H04N07/50

CPC classification number: H04N19/423 ,  H04N19/61

Abstract: According to the present invention circuitry is provided for processing digital data items. The circuitry comprises compression and decompression circuitry. The compression circuitry further comprises: a circuit for transforming M number of data items into N number of data items; a circuit for quantising P number of data items and producing Q number of data items; and a circuitry for appropriately storing in memory and/or transferring R number of data items. The decompression circuitry comprises: a circuit for appropriately retrieving from memory and/or receiving S number of data items; a circuit for dequantising T number of data items and producing U number of dequantised data items; and a circuit for receiving and inverse transforming V number of data items into W number of data items, said W data items being representative of said M data items.

Abstract translation: 根据本发明，提供了用于处理数字数据项的电路。 电路包括压缩和解压缩电路。 压缩电路还包括：用于将M个数据项变换成N个数据项的电路; 用于量化P个数据项并产生Q个数据项的电路; 以及用于适当地存储在存储器中和/或传送R个数据项的电路。 解压缩电路包括：用于从存储器适当地检索和/或接收S个数据项的电路; 用于逆量化T个数据项并产生U个解量化数据项的电路; 以及用于接收并将V个数据项逆变换为W个数据项的电路，所述W个数据项表示所述M个数据项。

公开(公告)号：WO1998009471A1

公开(公告)日：1998-03-05

申请号：PCT/GB1997002338

申请日：1997-08-29

Applicant: SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF

Inventor： SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF ,  SIMPSON, Robert ,  RICHARDS, Neil ,  THOMPSON, Peter ,  MONIOT, Pascal ,  COPPOLA, Marcello ,  DUMAS, Pierre ,  GRENOT, Thierry ,  MOUEN MAKOUA, David

IPC: H04Q11/04

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/1553 ,  H04L49/255 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5681 ,  H04Q11/0478

Abstract: An ATM routing switch for bidirectional transmission of at least two types of cell (61), one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity (160) for cells of the first type, a second reserve buffer capacity (150) for cells of said second type and control circuitry (39, 40, 41) for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity (160) is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity (150) has been reached by input of cells of said second type.

Abstract translation: 用于至少两种类型的小区（61）的双向传输的ATM路由交换机，接收可变比特率传输的一种类型和接收传输中的小区的一些丢失的第二类型，包括用于所述小区的小区的第一预备缓冲器容量（160） 第一类型，用于所述第二类型的单元的第二预留缓冲器容量（150）和用于产生流量控制信号（FCT）的控制电路（39,40,41），如果达到所述第一缓冲器容量（160）的预定阈值 通过输入所述第一类型的单元，并且如果通过所述第二类型的单元的输入已经达到了用于所述第二缓冲器容量（150）的预定阈值，则丢弃所述第二类型的输入单元。

公开(公告)号：WO1998009470A1

公开(公告)日：1998-03-05

申请号：PCT/GB1997002331

申请日：1997-08-29

Applicant: SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF

Inventor： SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF ,  SIMPSON, Robert ,  RICHARDS, Neil ,  THOMPSON, Peter ,  MONIOT, Pascal ,  COPPOLA, Marcello ,  COTTIGNIES, Vincent ,  DUMAS, Pierre ,  MOUEN MAKOUA, David

IPC: H04Q11/04

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/255 ,  H04L49/256 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04Q11/0478

Abstract: An ATM routing switch (21) has a buffer circuit (35) for holding cells located on queues at output ports (30), the buffer having a first reserve buffer capacity (161, 162) for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity (163, 164) for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity (150) for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

Abstract translation: ATM路由交换机（21）具有用于保存位于输出端口（30）上的队列上的小区的缓冲电路（35），该缓冲器具有用于要求单元格完整性的第一类型的单元的第一备用缓冲器容量（161,162） 传输和用于确定通过网络的允许路径的第一指定;第一类型的小区的第二预留缓冲器容量（163,164）具有用于确定网络中的不同允许路径的第二指定，以及第三 如果达到第一，第二或第三缓冲器容量的预定阈值，流量控制电路用于限制第一或第二类型的单元的输入，流量控制电路接收第二类型的单元的预留缓冲器容量（150） 。

公开(公告)号：US20020078330A1

公开(公告)日：2002-06-20

申请号：US09842312

申请日：2001-04-25

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Andrew C. Sturges ,  Nathan M. Sidwell

IPC: G06F009/00

CPC classification number: G06F9/3804 ,  G06F9/3842

Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Abstract translation: 描述用于执行分支指令的计算机系统和执行分支指令的方法。 两个指令取出器分别从存储器执行的指令序列和从执行的指令序列中的由设置的分支指令识别的目标位置开始的指令序列。 当产生效果分支信号时，接下来执行目标指令，并且获取执行指令的获取器开始获取目标指令。 效果分支信号与设定的分支指令分开产生。 在另一方面，效果分支信号是在执行位于要采用分支的指令序列中的点处的条件效果分支指令时产生的。

公开(公告)号：US20020002657A1

公开(公告)日：2002-01-03

申请号：US09924289

申请日：2001-08-08

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Andrew C. Sturges ,  David May

IPC: G06F012/00

CPC classification number: G06F12/126 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0888

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract translation: 在其中处理器能够执行多个处理的系统中描述了操作高速缓冲存储器的方法，每个处理包括一系列指令。 在该方法中，高速缓冲存储器被分为高速缓存分区，每个高速缓存分区具有多个可寻址存储位置，用于保存高速缓冲存储器中的项目。 分配指示符被分配给每个进程，标识哪个（如果有的话）所述高速缓存分区将用于保存用于执行该进程的项目。 当处理器在执行所述当前进程期间请求来自主存储器的项目并且该项目不被保存在高速缓冲存储器中时，该项目从主存储器中取出并被加载到所识别的高速缓存分区中的多个可寻址存储位置之一中。

公开(公告)号：JP4732554B2

公开(公告)日：2011-07-27

申请号：JP30117497

申请日：1997-10-31

Applicant: エスジーエス−トムソン マイクロエレクトロニクス リミテッドSgs−Thomson Microelectronics Limited

Inventor： マイケル ジョーンズ アンドリュー ,  アラン エドワーズ デビッド ,  デービッド メイ マイケル

IPC: G06F11/28 ,  G06F15/78 ,  G06F9/445 ,  G06F11/14 ,  G06F11/36

CPC classification number: G06F11/3648 ,  G06F9/4401 ,  G06F11/1417

公开(公告)号：JP4493739B2

公开(公告)日：2010-06-30

申请号：JP34988597

申请日：1997-12-19

Applicant: エスジーエス−トムソン マイクロエレクトロニクス リミテッドSgs−Thomson Microelectronics Limited

Inventor： ウォレン ロバート

IPC: G06F11/22 ,  G06F11/28 ,  G06F11/36

CPC classification number: G06F11/3648

公开(公告)号：JP3929572B2

公开(公告)日：2007-06-13

申请号：JP30095797

申请日：1997-10-31

Applicant: エスジーエス−トムソン マイクロエレクトロニクス リミテッドSgs−Thomson Microelectronics Limited

Inventor： ウォレン ロバート

IPC: G06F11/22 ,  G01R31/3185 ,  G06F15/78

CPC classification number: G01R31/318572

公开(公告)号：JP4504466B2

公开(公告)日：2010-07-14

申请号：JP30095897

申请日：1997-10-31

Applicant: エスジーエス−トムソン マイクロエレクトロニクス リミテッドSgs−Thomson Microelectronics Limited

Inventor： ウォレン ロバート

IPC: G06F11/30 ,  G06F11/36

CPC classification number: G06F11/3656

公开(公告)号：JP4426655B2

公开(公告)日：2010-03-03

申请号：JP4703098

申请日：1998-02-27

Applicant: エスジーエス−トムソン マイクロエレクトロニクス リミテッドSgs−Thomson Microelectronics Limited

Inventor： ウォレン ロバート

IPC: G01R31/28 ,  G06F11/22 ,  G06F11/28 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/348

Abstract: There is disclosed a single chip integrated circuit device including on-chip functional circuitry and a plurality of diagnostic units connected to monitor the on-chip functional circuitry. The plurality of diagnostic units detect respective trigger conditions by comparing signals from the on-chip functional circuitry with data held in respective diagnostic registers of the diagnostic units. The single chip integrated circuit device further includes trigger sequence control circuitry arranged to receive the trigger conditions and to initiate a trigger message when a predetermined sequence of the trigger conditions is detected. There is also disclosed a method of controlling such trigger sequences.