公开(公告)号：EP0526029B1

公开(公告)日：1997-03-05

申请号：EP92306412.5

申请日：1992-07-14

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Monk, Trevor Kenneth

IPC: G06F12/02 ,  G11C7/00

CPC classification number: G06F12/0215 ,  G11C7/00

公开(公告)号：EP0610064A2

公开(公告)日：1994-08-10

申请号：EP94300737.7

申请日：1994-02-01

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Hall, Andrew Medlicott ,  Monk, Trevor Kenneth

IPC: H03K17/16 ,  G05F3/24

CPC classification number: H03K17/163 ,  G05F3/242

Abstract: A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input (36) to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs (41,42) of similar specific transconductance operating at different drain current densities. Circuitry (51,52) is responsive to different gate voltages of the transistors (41,42) at the respective drain current densities to operate the signal (36).

Abstract translation: 用于FET晶体管的开关电路包括耦合到FET的栅极的受控电流电路。 受控电流电路的输入（36）表示FET的栅极电压的期望变化率，并且由响应于在不同漏极操作的具有类似特定跨导的两个FET（41,42）的平均特定跨导的电路 电流密度。 电路（51,52）响应于各个漏极电流密度处的晶体管（41,42）的不同栅极电压来操作信号（36）。

公开(公告)号：EP0610064A3

公开(公告)日：1994-11-23

申请号：EP94300737.7

申请日：1994-02-01

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Hall, Andrew Medlicott ,  Monk, Trevor Kenneth

IPC: H03K17/16 ,  G05F3/24

CPC classification number: H03K17/163 ,  G05F3/242

Abstract: A switching circuit for an FET transistor includes a controlled current circuit coupled to the gate of the FET. The input (36) to the controlled current circuit represents a desired rate of change of gate voltage of the FET and is generated by a circuit responsive to the average specific transconductance of two FETs (41,42) of similar specific transconductance operating at different drain current densities. Circuitry (51,52) is responsive to different gate voltages of the transistors (41,42) at the respective drain current densities to operate the signal (36).

Abstract translation: 用于FET晶体管的开关电路包括耦合到FET的栅极的受控电流电路。 受控电流电路的输入（36）表示FET的栅极电压的期望变化率，并且由响应于在不同漏极工作的类似特定跨导的两个FET（41,42）的平均特定跨导产生的电路产生 电流密度。 电路（51,52）以相应的漏极电流密度响应于晶体管（41,42）的不同栅极电压以操作信号（36）。

公开(公告)号：EP0526029A1

公开(公告)日：1993-02-03

申请号：EP92306412.5

申请日：1992-07-14

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Monk, Trevor Kenneth

IPC: G06F12/02 ,  G11C7/00

CPC classification number: G06F12/0215 ,  G11C7/00

Abstract: A memory is provided with at least one temporary store (21,22) and write abort circuitry (41,42) having a control signal store (41) and gating circuitry (43,44) responsive to an output from the control signal store. Write circuitry loads data and an associated address in the temporary store (21,22) during one write cycle and transfer circuitry (13,23) transfers the data to the associated address during a subsequent write cycle when the write operation is not to be aborted. Read circuitry includes a comparator (27) for comparing a read address with an address in the temporary store (22) and transfer circuitry includes selection circuitry (24) to select an output of data either from the temporary store (21) or the memory (11) dependent on the output of the comparator circuitry (27), an output from the temporary store (21) being prevented if the control signal store (41) indicates that the write operation is to be aborted.

Abstract translation: 存储器具有响应于来自控制信号存储器的输出的至少一个临时存储器（21,22）和写入中止电路（41,42），其具有控制信号存储器（41）和门控电路（43,44）。 写入电路在一个写入周期期间将数据和相关联的地址加载到临时存储器（21,22）中，并且当写入操作不被中止时，传送电路（13,23）在后续写入周期期间将数据传送到相关联的地址 。 读取电路包括用于将读取地址与临时存储器（22）中的地址进行比较的比较器（27），并且传送电路包括从临时存储器（21）或存储器（21）中选择数据输出的选择电路（24） 如果控制信号存储器（41）指示写操作被中止，则根据比较器电路（27）的输出，如果暂存器（21）的输出被阻止，则防止输出。