公开(公告)号：JP2002015564A

公开(公告)日：2002-01-18

申请号：JP2001158867

申请日：2001-05-28

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  GODUCHEAU OLIVIER

IPC: G11C11/401 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099

Abstract: PROBLEM TO BE SOLVED: To conduct data read out, which is less likely to be adversely affected by a leakage current by precharging reference cells. SOLUTION: Individual memory cells are connected to bit lines and are related to a main reference cell that is connected to a reference bit line. During the step in which memory cells are read and refreshed, the main reference cell and a subreference cell connected to the reference bit line and the bit lines are activated. Then, these two reference cells are deactivated and charged to a final precharge voltage, that is selected to become smaller than or larger than one half of the sum of a high state voltage and a low state voltage (depending on the utilization of NMOS technology or PMOS technology). This is performed by connecting the two reference cells to a capacitive line which is separated from the bit lines and the reference bit line and has a predetermined potential and a preset capacitance value.

公开(公告)号：FR2810150B1

公开(公告)日：2002-10-04

申请号：FR0007522

申请日：2000-06-13

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  GODUCHEAU OLIVIER

IPC: G11C11/401 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099

Abstract: The method of memory cell read access control has a memory cell (CM) connected to a bit line (BL) and having a reference cell (DCMP) connected to a reference line (BLN). During the read phase the reference cell and secondary reference (DCMS) are connected to the bit line and after deactivating the reference cells precharging the bit line to a precharge voltage above or below the final voltage.

公开(公告)号：FR2810150A1

公开(公告)日：2001-12-14

申请号：FR0007522

申请日：2000-06-13

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  GODUCHEAU OLIVIER

IPC: G11C11/401 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099

Abstract: The method of memory cell read access control has a memory cell (CM) connected to a bit line (BL) and having a reference cell (DCMP) connected to a reference line (BLN). During the read phase the reference cell and secondary reference (DCMS) are connected to the bit line and after deactivating the reference cells precharging the bit line to a precharge voltage above or below the final voltage.