Abstract:
PROBLEM TO BE SOLVED: To provide an access controller with a simple structure allowing reduction of peak power consumption. SOLUTION: This access controller controlling access to a data memory has: a means storing a plurality of attributes (ATi) for defining a right of the access to the data memory (DMEM); cache memories (CMEM, CMC) storing a prescribed number of attributes; and a synchronous attribute retrieval circuit (ASC2) retrieving the attribute inside the storage means (DMEM, ATMEM) when the attribute is absent inside the cache memory. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
The machine has a flip-flop (31) receiving a following sate code to provide a current state code (CSC) in synchronization with a clock signal. A current state decoder (33) has comparators comparing the code (CSC) and preset codes (SC0-SCk) by full scale decoding to provide identification signals to a NOR gate (35). The gate provides an error signal when the code (CSC) does not correspond to the preset codes having a hamming distance equal to 2. Independent claims are also included for the following: (A) an integrated circuit having state machines (B) a method of manufacturing a state machine of an integrated circuit.
Abstract:
The device has a cache memory that records attributes, and a dedicated zone (DZ) that stores attributes of a secured memory zone. An attribute search synchro loop intercepts the access control and reads the attribute in a data memory corresponding to the secured memory zone when the access control is sent to the data memory. The synchro loop applies the access control to the data memory. An independent claim is also included for a method for controlling access to a data memory.