UNIFORMLY INTEGRATED STORAGE DEVICE

    公开(公告)号:JPH07287985A

    公开(公告)日:1995-10-31

    申请号:JP29488294

    申请日:1994-11-29

    Abstract: PURPOSE: To install the row of OTP elements into the memory-element matrix of an electrically erasable storage device without the trouble of reliability and operation by mounting a field-effect transistor as an electronic switch between an OTP-element control line and a ground. CONSTITUTION: In the matrix of a user memory element, at least one row OTP1 or OTP2 of one-time programmable(OTP) element sharing a line selective line D1 -D5 with other elements is added. These OTP elements have selective terminals connected to the row selective lines OTP1 , OTP2 in the same manner as other memory elements. The source terminals of the OTP elements in the rows of the OTP1 , OTP2 are connected to a device ground (GND) through common switching transistors M1 , M2 driven from the same row selective line. Accordingly, since the selective transistors M1 , M2 are controlled from the OTP row decoding lines OTP1 , OTP2 , an additional external control signal is unnecessitated for driving the switching transistors M1 , M2 of the OTP elements.

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