公开(公告)号：JP2007226779A

公开(公告)日：2007-09-06

申请号：JP2007017827

申请日：2007-01-29

Applicant: St Microelectronics Srl ,  エスティマイクロエレクトロニクス ソシエタ ア レスポンサビリタ リミタータ

Inventor： PASOLINI FABIO ,  TRONCONI MICHELE

IPC: G06M3/00 ,  G01C22/00 ,  G01P15/00 ,  G01P15/18

CPC classification number: G01P15/125 ,  G01C22/006

Abstract: PROBLEM TO BE SOLVED: To reduce collision between a pedometer function and functions except the pedometer function. SOLUTION: An inertial device that is integratable in a portable electronic device includes: an inertial sensor (11) for generating at least one raw acceleration signal (S X , S Y , S Z ) in response to acceleration caused by movement of walking and running of a user of a pedometer; and a processing unit (12), associated to the inertial sensor (11) for counting the number of steps (N T ) of the user of the pedometer on the basis of the raw acceleration signal (S X , S Y , S Z ). The inertial sensor (11) and the processing unit (12) are both encapsulated within a single package for integrated circuits (13), which can be coupled to a circuit board (9) of an electronic device (1) and is provided with at least one connection terminal (13a) for making the number of steps (N T ) available to the outside world. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：减少计步器功能与计步器功能以外的功能之间的碰撞。 解决方案：在便携式电子设备中可积分的惯性装置包括：惯性传感器（11），用于产生至少一个原始加速度信号（S X ，S Y < SB>，S Z ），以响应由计步器的使用者的行走和跑步的运动引起的加速度; 以及与所述惯性传感器相关联的处理单元，所述惯性传感器用于根据所述原始加速度信号计数所述计步器的用户的步数（N T ）， SB> X ，S Y ，S Z ）。 惯性传感器（11）和处理单元（12）都被封装在用于集成电路（13）的单个封装内，其可以耦合到电子设备（1）的电路板（9）并且设置在 至少一个用于使外部世界可用的步骤数（N T ）的连接端子（13a）。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003208306A

公开(公告)日：2003-07-25

申请号：JP2002347918

申请日：2002-11-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CREMONESI ALESSANDRO ,  ROVATI FABRIZIO ,  PAU DANILO

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To provide a processing architecture capable of executing two or more different sets of instructions. SOLUTION: The architecture comprises a single CPU configured for executing both the instructions of the first set (OsTask1.1, OsTask1.2,...) and the instructions of the second set (MmTask2.1, MmTask2.2, MmTask2.3,...). The single CPU is configured for being switched between a first operating mode, in which the single CPU executes the first set instructions (OsTask1.1, OsTask1.2,...) and a second operating mode, in which the single CPU executes the second set of instructions (MmTask2.1, MmTask2.2, MmTask2.3,...). The solution can be generalized by the use of a plurality of switching instructions between more than two execution modes for different CPUs. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003198274A

公开(公告)日：2003-07-11

申请号：JP2002234488

申请日：2002-08-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

IPC: H03F1/34 ,  H03H11/48

Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a nonlinear passive element. SOLUTION: The circuit refers to nonlinear electronic equipment, especially in a nonlinear capacitor, more specifically, to the electronic circuit device that can be integrated on a semiconductor substrate (not limited). A nonlinear device is advantageously set to be a capacitor consisting of the feedback loop of a plurality of active blocks (2, 5, and 6), that are mutually subjected to cascade connection. Further, the invention can be integrated with or can be used relating to a network including other pieces of nonlinear device. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003153290A

公开(公告)日：2003-05-23

申请号：JP2002256394

申请日：2002-09-02

Applicant: ST MICROELECTRONICS SRL

Inventor： BOSCO ANGELO ,  MANCUSO MASSIMO

IPC: H04N9/07 ,  G06T5/00 ,  G06T5/20 ,  H04N5/217 ,  H04N9/04 ,  H04N101/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for preserving picture detail and applying filter processing to noise from complicated image files. SOLUTION: A filter is provided for a digital camera includes image sensors sensitive to light, a color filter placed over sensitive elements of the sensors and patterned according to a Bayer mosaic pattern layout, an interpolation algorithm joining together the digital information provided by differently colored adjacent pixels in the Bayer pattern. The filter (10) is adaptive and includes a noise level computation block (26) thus removing noise while simultaneously preserving picture detail.

公开(公告)号：JP2003142988A

公开(公告)日：2003-05-16

申请号：JP2002234482

申请日：2002-08-12

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  BETTI GIORGIO ,  CHRAPPAN SOLDAVINI FRANCESCO ,  HASSNER MARTIN AURELIANO

IPC: H01L21/822 ,  H01L27/04 ,  H03H11/48

Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a non-linear passive element. SOLUTION: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

公开(公告)号：JP2002229849A

公开(公告)日：2002-08-16

申请号：JP2001401897

申请日：2001-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： RIVA REGGIORI RICCARDO ,  SCHIPPERS STEFAN ,  SALI MAURO

IPC: G11C16/02 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/0893 ,  G11C7/10 ,  G11C16/26

Abstract: PROBLEM TO BE SOLVED: To reduce an average access time to a nonvolatile memory in a read- out phase. SOLUTION: In this method and device for reducing the average access time to the nonvolatile memory in the read-out phase, the read-out phase is generated from a matrix array 2 in a memory cell having a related logic for recognizing an access address to the memory both in a page mode and a burst mode. The method is characterized by providing a buffer memory 4 related to the cell matrix array 2, and housing memory words to the prescribed number (n) in the buffer memory 4 after the last read-out of the cell matrix array 2.

公开(公告)号：JP2002027437A

公开(公告)日：2002-01-25

申请号：JP2001111410

申请日：2001-04-10

Applicant: ST MICROELECTRONICS SRL

Inventor： BOLCIONI LUCA ,  GUERRIERI ROBERTO

IPC: B60S5/00 ,  G06F12/16 ,  H04N5/76 ,  H04N5/907 ,  H04N5/91 ,  H04N5/926 ,  H04N7/18

Abstract: PROBLEM TO BE SOLVED: To provide an event documentation system which can supply high- quality, sure, and guaranteed video recording when a certain event occurs. SOLUTION: This event documentation system is provided with a television camera (1) which acquires images and generates video signals and memory devices (4 and 5) which store the video signals. The system is also provided with a sensor (3) which enables the system to activate the storage of the video signals in the memory devices (4 and 5), and the devices (4 and 5) are respectively provided with a volatile first memory (4) and a nonvolatile second memory (5). The sensor (3) activates the transmission of the video signals to the nonvolatile memory (5) by means of the volatile memory (4).

公开(公告)号：JP2001358589A

公开(公告)日：2001-12-26

申请号：JP2001119402

申请日：2001-04-18

Applicant: ST MICROELECTRONICS SRL

Inventor： BARDELLI ROBERTO ,  TARANTOLA MARIO

IPC: H03M1/38 ,  H03M1/08 ,  H03M1/46

Abstract: PROBLEM TO BE SOLVED: To provide a successive approximation analog-digital conversion which functions well even when converting such analogue signal as changes slow into a digital signal. SOLUTION: The successive approximation analogue/digital converter which comprises a control logic circuit 1 time-controlled by an external clock signal comprises a digital/analogue converter 2 which converts a second digital D supplied from the control logic circuit into an analogue signal A, and a comparator 3 which compares the analogue signal A with an analogue signal B inputted into the analogue-digital converter. The analogue-digital converter is provided with devices 4 and 20 which increases the analogue signal A, by a preset value Voffs, which is outputted from the digital-analogue converter 2 and inputted in the comparator when the bit of first digital signal D1 that corresponds, by position, to the bit of second digital signal D which is required to be decided during clock cycle is zero.

公开(公告)号：JP2001229691A

公开(公告)日：2001-08-24

申请号：JP2000374346

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SRL

Inventor： MANSTRETTA ALESSANDRO ,  MICHELONI RINO ,  PIERIN ANDREA ,  YERO EMILIO

IPC: G06F12/16 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To obtain a non-volatile memory device having row redundancy being freely constituted in which correcting capability of architecture can be reconstituted for each chip. SOLUTION: This device comprises a row decoding circuit 12 and a column decoding circuit 13, a circuit reading out stored data in a memory cell and changing it, a memory matrix 14 which can store a fault row address, and a control circuit. The device also comprises a circuit comparing a fault row address stored in the memory matrix 14 with a selected row address in order to recognize a selected row address ADr and perform relieving selection of a fault row and selection of a corresponding redundant cell row at the time of recognizing validness, and configuration register comprising a matrix of a non-volatile memory cell and a control circuit.

公开(公告)号：JP2001189662A

公开(公告)日：2001-07-10

申请号：JP2000349015

申请日：2000-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： PAU DANILO ,  BORTOT LUCA ,  SACCHI MARIA LUISA

IPC: G06T9/00 ,  H03M7/30 ,  H03M7/40 ,  H04N7/26

Abstract: PROBLEM TO BE SOLVED: To provide technology for easily changing the bit rate of the data stream of a video picture. SOLUTION: An input bit stream is divided into the sequence of encoded data and the sequence of a control bit. The output sequence of the control bit is generated by correcting the sequence of the control bit by the function of a different bit rate in a desired output bit stream. The intermediate sequence of data is generated by decoding the sequence of the code data. The output sequence of the encoded data is generated by quantizing data in a previously established step and encoding the intermediate data of these data. These output sequences are joined and the output stream having the desired bit rate is generated.