公开(公告)号：EP1624704A2

公开(公告)日：2006-02-08

申请号：EP05016383.1

申请日：2005-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Sarkar, Abhik ,  Maiti, Srijib Narayan

IPC: H04N7/50 ,  G06T9/00

CPC classification number: H04N19/436 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.

Abstract translation: 在并行处理环境中的视频解码器的宏块级并行实现，包括可变长度解码（VLD）块，以解码编码的离散余弦变换（DCT）系数; 接收所述解码的离散余弦变换（DCT）系数的主节点; 以及用于在宏块级别并行实现逆离散余弦变换（IDCT）和运动补偿的多个从属节点/处理器。

公开(公告)号：EP1624704B1

公开(公告)日：2010-03-31

申请号：EP05016383.1

申请日：2005-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Sarkar, Abhik ,  Maiti, Srijib Narayan

IPC: H04N7/50 ,  G06T9/00

CPC classification number: H04N19/436 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

公开(公告)号：EP1624704A3

公开(公告)日：2008-09-10

申请号：EP05016383.1

申请日：2005-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Sarkar, Abhik ,  Maiti, Srijib Narayan

IPC: H04N7/50 ,  G06T9/00

CPC classification number: H04N19/436 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.