公开(公告)号：EP1447752A3

公开(公告)日：2006-02-22

申请号：EP04100617.2

申请日：2004-02-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Narayan, Srijib

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.

公开(公告)号：EP1624704B1

公开(公告)日：2010-03-31

申请号：EP05016383.1

申请日：2005-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Sarkar, Abhik ,  Maiti, Srijib Narayan

IPC: H04N7/50 ,  G06T9/00

CPC classification number: H04N19/436 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

公开(公告)号：EP1538533A3

公开(公告)日：2006-02-22

申请号：EP04106295.1

申请日：2004-12-03

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Maiti, Srijib Narayan ,  Cornero, Marco

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: An improved FFT / IFFT processor comprising computation means capable of processing butterfly operations, and storage means for storing the operands of butterfly operations, and a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations, and wherein the computation means is capable of simultaneously accessing and processing said multiple butterfly operations.

公开(公告)号：EP1624704A2

公开(公告)日：2006-02-08

申请号：EP05016383.1

申请日：2005-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Sarkar, Abhik ,  Maiti, Srijib Narayan

IPC: H04N7/50 ,  G06T9/00

CPC classification number: H04N19/436 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.

Abstract translation: 在并行处理环境中的视频解码器的宏块级并行实现，包括可变长度解码（VLD）块，以解码编码的离散余弦变换（DCT）系数; 接收所述解码的离散余弦变换（DCT）系数的主节点; 以及用于在宏块级别并行实现逆离散余弦变换（IDCT）和运动补偿的多个从属节点/处理器。

公开(公告)号：EP1624704A3

公开(公告)日：2008-09-10

申请号：EP05016383.1

申请日：2005-07-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Sarkar, Abhik ,  Maiti, Srijib Narayan

IPC: H04N7/50 ,  G06T9/00

CPC classification number: H04N19/436 ,  H04N19/433 ,  H04N19/44 ,  H04N19/51 ,  H04N19/61

Abstract: A macro-block level parallel implementation of a video decoder in parallel processing environment comprising a Variable Length Decoding (VLD) block to decode the encoded Discrete Cosine Transform (DCT) coefficient; a master node which receives said decoded Discrete Cosine Transform (DCT) coefficients; and, plurality of slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at macro-block level.

公开(公告)号：EP1538533A2

公开(公告)日：2005-06-08

申请号：EP04106295.1

申请日：2004-12-03

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Maiti, Srijib Narayan ,  Cornero, Marco

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: An improved FFT / IFFT processor comprising computation means capable of processing butterfly operations, and storage means for storing the operands of butterfly operations, and a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations, and wherein the computation means is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract translation: 一种改进的FFT / IFFT处理器，包括能够处理蝶形运算的计算装置和用于存储蝶形运算的操作数的存储装置，以及用于在连续的存储位置存储多个连续的蝶形运算的操作数的机构，并且其中计算装置能够 同时访问和处理所述多个蝴蝶操作。

公开(公告)号：EP1447752A2

公开(公告)日：2004-08-18

申请号：EP04100617.2

申请日：2004-02-16

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Saha, Kaushik ,  Narayan, Srijib

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: The present invention provides a scalable method for implementing FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements, comprising computing each butterfly of the first "log 2 P" stages on either a single processor or each of the "P" processors simultaneously and distributing the computation of the butterflies in all the subsequent stages among the "P" processors such that each chain of cascaded butterflies consisting of those butterflies that have inputs and outputs connected together, are processed by the same processor.
The invention also provides a system for obtaining scalable implementation of FFT/IFFT computations in multiprocessor architectures that provides improved throughput by eliminating the need for inter-processor communication after the computation of the first "log 2 P" stages for an implementation using "P" processing elements.

Abstract translation: 本发明提供一个可扩展的方法，用于在多处理器体系结构实现FFT / IFFT计算确实由第一“日志2 P”阶段的计算后消除了对处理器间通信的需要提供改进的吞吐量在实施使用“P”的处理元件 ，包括同时计算在任一单个处理器或每个“P”处理器的第一“日志2 P”阶段，每个阶段蝴蝶和分发寻求做各链中的“P”的处理器之间的所有后续阶段中的蝴蝶的计算 的级联蝴蝶由...组成这些蝴蝶thathave连接在一起的输入和输出，通过相同的处理器处理。 因此本发明提供一种系统，用于在多处理器体系结构获得可扩展的实施FFT / IFFT计算的那样通过在实施使用“P”消除了对处理器间通信的需要的第一个“登录2 P”阶段的计算后提供改进的吞吐量 处理元件。