公开(公告)号：WO2005117402A1

公开(公告)日：2005-12-08

申请号：PCT/IT2005/000281

申请日：2005-05-19

Applicant: STMICROELECTRONICS S.R.L. ,  NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

Abstract translation: 描述了一种用于从数字信号和宽带传输系统重建模拟信号的电路，特别是用于蜂窝电话系统中的用途，或更一般地在采用WCDMA标准的移动通信系统中。 该电路包括：适于接收所述数字信号并将其转换为模拟信号的数模转换器（DAC）; - 低通滤波器（LOW-PASS），连接在所述转换器的输出端，用于以模拟格式接收所述信号，并提供所述重构模拟信号的输出。 有利地，低通滤波器（LOW-PASS）是连续的数字模拟转换器（DAC）的输出端的时间和电流连续的有源滤波器，并且数模转换器（DAC）是电流转向器 在大于待重构的所述模拟信号的奈奎斯特频率的采样频率下工作。

公开(公告)号：WO2003007479A1

公开(公告)日：2003-01-23

申请号：PCT/EP2002/006487

申请日：2002-06-13

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23"). A logic unit (17") controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23"). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.

Abstract translation: 以二进制码加权的采样电容器的第一阵列（10A'）的电容器连接在第一公共电路节点（NB +）和要被充电到相对于地的电压（Vin）的输入端子（Gnd）之间 然后根据BAR技术选择性地连接两个差分参考端（Vrefp，Vrefm），同时将第一阵列（10B'）的电容等于第一阵列（10B'），并将其全部连接到 第二节点（NB-）选择性地连接到地（Gnd）和下差分电压端（Vrefm）。 两个节点连接到比较器（23“）的相应输入端，逻辑单元（17”）根据预定的定时程序控制两个阵列的电容器的连接，并根据 比较器（23“）虽然转换器具有单端输入，但它的作用就像具有差分输入的转换器20，因此在噪声方面具有优异的抗扰度，而且不需要额外的电容器或特别敏感的 比较器，其特征在于低功耗和高速度，占据其形成部分的集成电路的非常小的面积。

公开(公告)号：WO2008026228A1

公开(公告)日：2008-03-06

申请号：PCT/IT2006/000629

申请日：2006-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 描述了用于从差分转换为单端的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大器级（2） 差动级的第一（5）和不同的第二充电电路（6），其可以分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合。 该电路还包括第一（7）和第二（8）缓冲电路，每个功能性地布置在所述输出端之一之间和所述充电电路之一之间。 缓冲器电路被配置为使得朝着所述输出（OUT *，AUXOUT *）看到的相对阻抗之间的差异最小化。

公开(公告)号：WO2003012983A1

公开(公告)日：2003-02-13

申请号：PCT/EP2002/007524

申请日：2002-07-05

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  NICOLLINI, Germano ,  MARTIGNONE, Riccardo

Inventor： CONFALONIERI, Pierangelo ,  NICOLLINI, Germano ,  MARTIGNONE, Riccardo

IPC: H03F3/45

CPC classification number: H03F3/45937 ,  H03F1/303

Abstract: The circuit comprises a differential amplifier (10) with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal (INCM) of the amplifier and the outputs there are connected a first (C1p) and a second (1m) capacitor and first (C3) and second (C4) capacitive means that by means of controlled switches (SW9-SW12) can be alternatively and simultaneousy connected in parallel with, respectively, the first ((C1p) and the second (C1m) capacitor or between a first (VB) and a second (Vref1) reference voltage terminal. The capacitances C3 and C4 may be different in value such as to satisfy the following equality: Vcmn = Vref1 + '(Vrefp-Vrefm)/2!* (C4-C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref1 is the voltage of the second reference terminal.are chosen in such a way as to satisfy the following equality : Vcmn = Vref1 + [(Vrefp-Vrefm)/2] * (C4-C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref1 is the voltage of the second reference terminal.

Abstract translation: 该电路包括具有两个输入和两个输出的差分放大器（10）和一个共模调节电路。 在放大器的调节端子（INCM）和输出端之间连接有第一（C1p）和第二（1m）电容器以及通过受控开关（SW9-SW12）的第一（C3）和第二（C4）电容装置 ）可以分别与第一（（C1p）和第二（C1m）电容器或第一（VB）和第二（Vref1）参考电压端子并联连接，电容C3和C4可以是 不同的值，以满足以下等式：Vcmn = Vref1 +'（Vrefp-Vrefm）/ 2！*（C4-C3）/（C3 + C4），其中Vcmn是期望的共模输出电压，Vrefp和Vrefm 是差分输出电压，Vref1是第二参考端子的电压，以满足以下等式的方式选择：Vcmn = Vref1 + [（Vrefp-Vrefm）/ 2] *（C4-C3）/（ C3 + C4），其中Vcmn是所需的共模输出电压，Vrefp和Vrefm是差分输出电压，Vref1是秒的电压 参考端子。

公开(公告)号：EP1405419B1

公开(公告)日：2005-08-31

申请号：EP02743185.7

申请日：2002-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23"). A logic unit (17") controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23"). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.

公开(公告)号：EP2057735A1

公开(公告)日：2009-05-13

申请号：EP06796270.4

申请日：2006-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN') input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

公开(公告)号：EP1751963B1

公开(公告)日：2009-05-13

申请号：EP05750127.2

申请日：2005-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74 ,  H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

公开(公告)号：EP1751963A1

公开(公告)日：2007-02-14

申请号：EP05750127.2

申请日：2005-05-19

Applicant: STMicroelectronics S.r.l.

Inventor： NICOLLINI, Germano ,  CONFALONIERI, Pierangelo ,  MARTIGNONE, Riccardo

IPC: H04M1/74 ,  H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format; - a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current­ coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.

公开(公告)号：EP1405419A1

公开(公告)日：2004-04-07

申请号：EP02743185.7

申请日：2002-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23'). A logic unit (17') controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23'). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.