公开(公告)号：WO2008026228A1

公开(公告)日：2008-03-06

申请号：PCT/IT2006/000629

申请日：2006-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 描述了用于从差分转换为单端的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大器级（2） 差动级的第一（5）和不同的第二充电电路（6），其可以分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合。 该电路还包括第一（7）和第二（8）缓冲电路，每个功能性地布置在所述输出端之一之间和所述充电电路之一之间。 缓冲器电路被配置为使得朝着所述输出（OUT *，AUXOUT *）看到的相对阻抗之间的差异最小化。

公开(公告)号：WO2008023395A1

公开(公告)日：2008-02-28

申请号：PCT/IT2006/000628

申请日：2006-08-25

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  NICOLLINI, Germano ,  MINUTI, Alberto

IPC: H03F3/00

CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

Abstract translation: 描述了一种用于开关容量电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有输出电压（OUT），该输出电压取决于可由源极（1）提供的输入电压（VIN） ）到缓冲装置; - 可以分别在其连接的第一和第二状态之间切换到电源和电容缓冲器以将输入电压传送到输出端的电容性开关部件（C SUB） 所述部件设置有具有相关联的杂散能力（C P1）的端子（N2）。 该装置还包括一个充电和放电装置（SW＆lt; CPIR＆gt;，＆lt;＆gt; G＆gt;），其被配置为在占用第二个参考电压之前对参考电压（REFM）预充电杂散容量 条件，并且在摄取第一个条件之前预先排出杂散容量。

公开(公告)号：WO2003007479A1

公开(公告)日：2003-01-23

申请号：PCT/EP2002/006487

申请日：2002-06-13

Applicant: STMICROELECTRONICS S.R.L. ,  CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23"). A logic unit (17") controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23"). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.

Abstract translation: 以二进制码加权的采样电容器的第一阵列（10A'）的电容器连接在第一公共电路节点（NB +）和要被充电到相对于地的电压（Vin）的输入端子（Gnd）之间 然后根据BAR技术选择性地连接两个差分参考端（Vrefp，Vrefm），同时将第一阵列（10B'）的电容等于第一阵列（10B'），并将其全部连接到 第二节点（NB-）选择性地连接到地（Gnd）和下差分电压端（Vrefm）。 两个节点连接到比较器（23“）的相应输入端，逻辑单元（17”）根据预定的定时程序控制两个阵列的电容器的连接，并根据 比较器（23“）虽然转换器具有单端输入，但它的作用就像具有差分输入的转换器20，因此在噪声方面具有优异的抗扰度，而且不需要额外的电容器或特别敏感的 比较器，其特征在于低功耗和高速度，占据其形成部分的集成电路的非常小的面积。

公开(公告)号：EP2057735A1

公开(公告)日：2009-05-13

申请号：EP06796270.4

申请日：2006-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN') input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

公开(公告)号：EP1405419A1

公开(公告)日：2004-04-07

申请号：EP02743185.7

申请日：2002-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： CONFALONIERI, Pierangelo ,  ZAMPROGNO, Marco ,  NAGARI, Angelo

IPC: H03M1/06

CPC classification number: H03M1/0682 ,  H03M1/468 ,  H03M1/804

Abstract: The capacitors of a first array (10A') of sampling capacitors weighted in binary code are, connected between a first common circuit node (NB+) and an input terminal to be charged to the voltage (Vin) with respect to ground (Gnd) of a signal to be converted, and in accordance with BAR technique are then selectively connected with two differential reference terminals (Vrefp, Vrefm) .At the same time the capacitors of a second array (10B') equal to the first and all connected to a second node (NB-) are selectively connected to ground (Gnd) and the lower differential voltage terminal (Vrefm). The two nodes are connected to the respective inputs of a comparator (23'). A logic unit (17') controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator (23'). Though the converter has a single-ended input, it behaves like a converter 20 with a differential input and therefore has an excellent immunity with respect to noise. Furthermore, it does not need either additional capacitors or a particularly sensitive comparator, so that it is characterized by low consumption and high speed and occupies a very small area of the integrated circuit of which it forms part.

公开(公告)号：EP3758170A3

公开(公告)日：2021-04-21

申请号：EP20179464.1

申请日：2020-06-11

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco ,  TAJFAR, Alireza

IPC: H01S5/042 ,  H01S5/062 ,  H03K17/0814 ,  H03K17/10 ,  H01S5/068

Abstract: A circuit (20,20',20") includes a capacitance (Cvhv) coupled between a high voltage node (VHV) and ground, a laser diode (LD) having an anode coupled to the high voltage node (VHV) and a cathode coupled to an output node (OUT), and a current source (40) coupled between the output node (OUT) and ground. The current source (40) turns on based on assertion of a trigger signal and sinks current from the capacitance (Cvhv) to ground to thereby cause the laser diode (LD) to lase, and turns off based on deassertion of the trigger signal. A clamping circuit (22) is coupled between the output node (OUT) and the high voltage node (VHV), and clamps voltage at the output node (OUT) occurring when the current source (40) switches off.

公开(公告)号：EP4326038A1

公开(公告)日：2024-02-21

申请号：EP23188320.8

申请日：2023-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco ,  FURCERI, Raffaele Enrico ,  GIANOLLO, Matteo ,  LANGFELDER, Giacomo

IPC: H10N30/80

Abstract: A differential piezoelectric actuator-system (10) includes an inductor (L) and driver-circuit (11, 12) having switches (S1-S6) for transferring energy between first and second actuators (PZT1, PZT2) and the inductor, and between a voltage-supply node (Vbatt) and the inductor. Control circuitry (21) determines whether a next phase in which to operate the driver-circuit is a first charging-phase or a first recovery-phase. The first charging-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the voltage supply node to the inductor; and a third sub-phase to transfer energy from the inductor to the second actuator. The first recovery-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the inductor to the voltage supply node; and a third sub-phase to transfer energy from the inductor to the second actuator.

公开(公告)号：EP4207571A1

公开(公告)日：2023-07-05

申请号：EP22213961.0

申请日：2022-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： BARBIERI, Andrea ,  VIDONI, Aldo ,  ZAMPROGNO, Marco

IPC: H02M3/157 ,  H02M1/00

Abstract: A DC-DC boost converter includes an inductor (L) coupled between an input voltage (Vin) and an input node (Nn), a diode (D1) coupled between the input node and an output node (No), and an output capacitor (C1) coupled between the output node and ground such that an output voltage (VBOOST) is formed across the output capacitor. A switch (Sw) selectively couples the input node to ground in response to a drive signal (Vdrive). Control loop circuitry (Vfbk, 15') includes an error amplifier (17') to generate an analog error voltage (Verr) based upon a comparison of a feedback voltage (Vfbk) to a reference voltage (Vref), the feedback voltage being indicative of the output voltage, a quantizer (21) to quantize the analog error voltage to produce a digital error signal (Err), and a drive voltage generation circuit (22) to generate the drive signal as having a duty cycle based upon the digital error signal.

公开(公告)号：EP3913345A1

公开(公告)日：2021-11-24

申请号：EP21171960.4

申请日：2021-05-04

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco ,  BARBIERI, Andrea ,  FLORA, Pasquale ,  FURCERI, Raffaele Enrico

IPC: G01L9/04

Abstract: A bridge driver circuit (104) applies a bias voltage across first (142) and second (144) input nodes of a resistive bridge circuit (102) configured to measure a physical property such as pressure or movement. A sensing circuit (185) senses a bridge current (Ipbridge, Inbridge) that flows through the resistive bridge circuit (102) in response to the applied bias voltage. A temperature dependent sensitivity of the resistive bridge circuit (102) is determined by processing the sensed bridge current. A voltage output at first (146) and second (148) output nodes of the resistive bridge circuit (102) is processed to determine a value of the physical property. This processing further involves applying a temperature correction in response to the determined temperature dependent sensitivity.

公开(公告)号：EP3687068A1

公开(公告)日：2020-07-29

申请号：EP20151638.2

申请日：2020-01-14

Applicant: STMicroelectronics S.r.l.

Inventor： ZAMPROGNO, Marco

IPC: H03K17/687 ,  H03K4/02

Abstract: A method, comprising:
- providing a load capacitance (C L ) having a charge node (104);
- providing a set of energy storage capacitances (C 1 ), having respective charge nodes (101);
- providing electronic switch circuitry (20) configured to be made selectively conductive to couple the charge node (104) of the load capacitance (C L ) to respective charge nodes (101) of energy storage capacitances (C 1 ) in the set of energy storage capacitances (C 1 ), wherein the electronic switch circuitry (20) comprise a switched current path (T, L) through a first transistor (TT 1 ) and a second transistor (TT 2 ) including junction diodes (BD1, BD2), wherein the first transistor (TT 1 ) has a current path therethrough between a first common node (SS) and the respective charge node (101) of an energy storage capacitance (C 1 ) in the set of energy storage capacitances (C 1 , C 2 ) and the second transistor (TT 2 ) has a current path therethrough between the first common node (SS) and the charge node (104) of the load capacitance (C L ), the first transistor (TT 1 ) and the second transistor (TT 2 ) having control terminals mutually coupled at a second common node (GG), the control terminals having a parasitic capacitance (C P ). The method comprises pre-charging the parasitic capacitance (C P ) of the control terminals of the first transistor (TT 1 ) and the second transistor (TT 2 ) mutually coupled at the second common node (GG) prior to making conductive the switched current path (T, L) through the first transistor (TT 1 ) and the second transistor (TT 2 ).