公开(公告)号：EP4376298A1

公开(公告)日：2024-05-29

申请号：EP23208335.2

申请日：2023-11-07

Applicant: STMicroelectronics S.r.l.

Inventor： CURINA, Carlo ,  BENDOTTI, Valerio

IPC: H03K3/0233 ,  H03K3/013 ,  H04L25/02

CPC classification number: H03K3/02335 ,  H03K3/013 ,  H04L25/0266 ,  H04L25/0272

Abstract: In an electronic device (10), a pulse generator (11) receives an input signal (tx_com) and a clock signal (clk) and produces a transmission signal (tx_in) that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter (102) produces, at its two output nodes, a replica (com_p) of the transmission signal and the complement (com_n) of the transmission signal. A galvanic isolation barrier (103P, 103N) is coupled to the output nodes of the transmitter and produces a differential signal (Vd) that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal. A first comparator (42) produces an intermediate set signal (set_inn) that includes a pulse at each positive spike of the differential signal. A second comparator (44) produces an intermediate reset signal (reset_inn) that includes a pulse at each negative spike of the differential signal. A final set signal (setn) is produced by activating masking of the intermediate set signal in response to a pulse of the intermediate reset signal, and de-activating said masking in response to the end of a pulse of the intermediate set signal or in response to a time interval (Tdly3) elapsing after a pulse of the intermediate reset signal. A final reset signal (resetn) is produced by activating masking of the intermediate reset signal in response to a pulse of the intermediate set signal, and de-activating masking of the intermediate reset signal in response to the end of a pulse of the intermediate reset signal or in response to a time interval elapsing after a pulse of the intermediate set signal. An output control circuit (46) asserts an output signal (rx_com) in response to a pulse of the final set signal and de-asserts the output signal in response to a pulse of the final reset signal.

公开(公告)号：EP4113845A1

公开(公告)日：2023-01-04

申请号：EP22178676.7

申请日：2022-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： BENDOTTI, Valerio ,  DE CAMPO, Nicola ,  CURINA, Carlo

IPC: H03K19/0185 ,  H04L25/02

Abstract: A transmitter circuit (802') receives a PWM input signal ( PWM IN ) and a clock signal ( CLK ) . A logic circuit (805) generates a control signal ( TX DIS ) as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than half clock period of the clock signal. A tri-state transmitter (802) receives the PWM input signal and the control signal, and produces a first ( OUT P ) and a second ( OUT N ) output signals at a first (802P) and a second (802N) transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage ( V DD ) and a reference voltage ( V SS ) . An output control circuit (806) is sensitive to the control signal and is coupled to the first and second transmitter output nodes. In response to the control signal being high, the tri-state transmitter sets the first and second transmitter output nodes to a high impedance state, and the output control circuit drives the first and second transmitter output nodes to an intermediate voltage ( V X ) between the positive voltage and the reference voltage. In response to the control signal being low, the tri-state transmitter drives the first transmitter output node according to the logic value of the PWM input signal, and drives the second transmitter output node according to the inverted logic value of the PWM input signal. The tri-state transmitter is faster than the output control circuit in driving the first and second transmitter output nodes.