公开(公告)号：EP4207613A1

公开(公告)日：2023-07-05

申请号：EP22211470.4

申请日：2022-12-05

Applicant: STMicroelectronics S.r.l.

Inventor： BENDOTTI, Valerio ,  GENNARI SANTORI, Valerio

IPC: H04B3/00 ,  H02M3/00

Abstract: An isolated driver device (10) comprises a first semiconductor die (10a) and a second semiconductor die (10b) galvanically isolated from each other. The second semiconductor die (10b) includes a signal modulator circuit (122) configured to modulate a carrier signal to produce a modulated signal ( FB ) encoding information. A galvanically isolated communication channel (113', 111P', 111N', 110') implemented in the first semiconductor die (10a) and the second semiconductor die (10b) is configured to transmit the modulated signal ( FB ) from the second semiconductor die (10b) to the first semiconductor die (10a). The second semiconductor die (10b) includes: a fault detection circuit (118) configured to detect electrical faults in the second semiconductor die (10b); a logic circuit (114) coupled to the fault detection circuit (118) and configured to assert a modulation bypass signal ( BP ) in response to a fault being detected by the fault detection circuit (118); and modulation masking circuitry (123) configured to force the modulated signal ( FB ) to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal ( BP ) being asserted. The first semiconductor die (10a) includes a respective logic circuit (108) sensitive to the modulated signal ( FB , MOD) and configured to detect a condition where the modulated signal ( FB ) has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal ( FAULT ) in response to the condition being detected.

公开(公告)号：EP4376298A1

公开(公告)日：2024-05-29

申请号：EP23208335.2

申请日：2023-11-07

Applicant: STMicroelectronics S.r.l.

Inventor： CURINA, Carlo ,  BENDOTTI, Valerio

IPC: H03K3/0233 ,  H03K3/013 ,  H04L25/02

CPC classification number: H03K3/02335 ,  H03K3/013 ,  H04L25/0266 ,  H04L25/0272

Abstract: In an electronic device (10), a pulse generator (11) receives an input signal (tx_com) and a clock signal (clk) and produces a transmission signal (tx_in) that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter (102) produces, at its two output nodes, a replica (com_p) of the transmission signal and the complement (com_n) of the transmission signal. A galvanic isolation barrier (103P, 103N) is coupled to the output nodes of the transmitter and produces a differential signal (Vd) that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal. A first comparator (42) produces an intermediate set signal (set_inn) that includes a pulse at each positive spike of the differential signal. A second comparator (44) produces an intermediate reset signal (reset_inn) that includes a pulse at each negative spike of the differential signal. A final set signal (setn) is produced by activating masking of the intermediate set signal in response to a pulse of the intermediate reset signal, and de-activating said masking in response to the end of a pulse of the intermediate set signal or in response to a time interval (Tdly3) elapsing after a pulse of the intermediate reset signal. A final reset signal (resetn) is produced by activating masking of the intermediate reset signal in response to a pulse of the intermediate set signal, and de-activating masking of the intermediate reset signal in response to the end of a pulse of the intermediate reset signal or in response to a time interval elapsing after a pulse of the intermediate set signal. An output control circuit (46) asserts an output signal (rx_com) in response to a pulse of the final set signal and de-asserts the output signal in response to a pulse of the final reset signal.

公开(公告)号：EP4134688A2

公开(公告)日：2023-02-15

申请号：EP22186502.5

申请日：2022-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  BENDOTTI, Valerio ,  FINAZZI, Luca ,  BAGNATI, Gaudenzia

IPC: G01R31/42 ,  H02M3/158 ,  H02M1/32

Abstract: A circuit, comprising: a high-side transistor pair (S 0H , HS) and a low-side transistor pair (S 0L , LS) having a common intermediate node (OUT S, OUT), wherein the high-side transistor pair (S 0H , HS) comprises a first transistor (HS) having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node (OUT_D) and the intermediate node (OUT_S, OUT) as well as a second transistor (S 0H ) having a current flowpath therethrough coupled to the control node of the first transistor (HS), wherein the low-side transistor pair (S 0L , LS) comprises a third transistor (LS) having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node (OUT, OUT_S) and the reference voltage node (PGND) as well as a fourth transistor (S 0L ) having a current flowpath therethrough coupled to the control node of the third transistor (LS). The circuit comprises testing circuitry (40; 50) comprising a test-mode node (TM) configured to receive a test-mode signal (V TM ), the testing circuitry (40; 50) configured to be coupled to at least one of the second transistor (S 0H ) in the high-side transistor pair (S 0H , HS) and of the fourth transistor (S 0L ) in the low-side transistor pair (S 0L , LS) to apply thereto the test-mode signal (V TM ) wherein the at least one of the high-side transistor pair (S 0H , HS) and the low-side transistor pair (S 0L , LS) is made selectively conductive or non-conductive based on the test-mode signal (V TM ).

公开(公告)号：EP4113845A1

公开(公告)日：2023-01-04

申请号：EP22178676.7

申请日：2022-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： BENDOTTI, Valerio ,  DE CAMPO, Nicola ,  CURINA, Carlo

IPC: H03K19/0185 ,  H04L25/02

Abstract: A transmitter circuit (802') receives a PWM input signal ( PWM IN ) and a clock signal ( CLK ) . A logic circuit (805) generates a control signal ( TX DIS ) as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than half clock period of the clock signal. A tri-state transmitter (802) receives the PWM input signal and the control signal, and produces a first ( OUT P ) and a second ( OUT N ) output signals at a first (802P) and a second (802N) transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage ( V DD ) and a reference voltage ( V SS ) . An output control circuit (806) is sensitive to the control signal and is coupled to the first and second transmitter output nodes. In response to the control signal being high, the tri-state transmitter sets the first and second transmitter output nodes to a high impedance state, and the output control circuit drives the first and second transmitter output nodes to an intermediate voltage ( V X ) between the positive voltage and the reference voltage. In response to the control signal being low, the tri-state transmitter drives the first transmitter output node according to the logic value of the PWM input signal, and drives the second transmitter output node according to the inverted logic value of the PWM input signal. The tri-state transmitter is faster than the output control circuit in driving the first and second transmitter output nodes.

公开(公告)号：EP3648275A1

公开(公告)日：2020-05-06

申请号：EP19205311.4

申请日：2019-10-25

Applicant: STMicroelectronics S.r.l.

Inventor： D'ANGELO, Vittorio ,  CANNAVACCIUOLO, Salvatore ,  LECCE, Sergio ,  BENDOTTI, Valerio ,  PENNISI, Orazio

IPC: H02H9/00 ,  H02H9/04

Abstract: An integrated circuit with hot-plug protection is disclosed.
The integrated circuit (30) comprises a plurality of input pins (Pin1, ..., PinN) and at least one output pin (46), and includes a hot-plug protection circuit (40) .
The hot-plug protection circuit (40) comprises:
- a plurality of electrical connections, wherein the input pins in the plurality of input pins (Pin1, ..., PinN) are electrically coupled to a common node (42) in the hot-plug protection circuit (40) via respective electrical connections in the plurality of electrical connections, and
- clamping circuitry (44) coupled between the common node (42) and the at least one output pin (46), the clamping circuitry (44) activatable as a result of a voltage spike applied across the clamping circuitry (44) .
The plurality of electrical connections and the clamping circuitry (44) provide respective current discharge paths between the input pins in the plurality of input pins (Pin1, ..., PinN) and the at least one output pin (46), the respective current discharge paths configured to become conductive as a result of a voltage spike applied to any of said input pins in the plurality of input pins (Pin1, ..., PinN) being transferred to the common node (42) via the respective electrical connection in the plurality of electrical connections electrically coupling said any of said input pins to the common node (42).

公开(公告)号：EP4134688A3

公开(公告)日：2023-03-01

申请号：EP22186502.5

申请日：2022-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  BENDOTTI, Valerio ,  FINAZZI, Luca ,  BAGNATI, Gaudenzia

IPC: H02M3/158 ,  H02M1/32 ,  G01R31/42

Abstract: A circuit, comprising: a high-side transistor pair (S 0H , HS) and a low-side transistor pair (S 0L , LS) having a common intermediate node (OUT S, OUT), wherein the high-side transistor pair (S 0H , HS) comprises a first transistor (HS) having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node (OUT_D) and the intermediate node (OUT_S, OUT) as well as a second transistor (S 0H ) having a current flowpath therethrough coupled to the control node of the first transistor (HS), wherein the low-side transistor pair (S 0L , LS) comprises a third transistor (LS) having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node (OUT, OUT_S) and the reference voltage node (PGND) as well as a fourth transistor (S 0L ) having a current flowpath therethrough coupled to the control node of the third transistor (LS). The circuit comprises testing circuitry (40; 50) comprising a test-mode node (TM) configured to receive a test-mode signal (V TM ), the testing circuitry (40; 50) configured to be coupled to at least one of the second transistor (S 0H ) in the high-side transistor pair (S 0H , HS) and of the fourth transistor (S 0L ) in the low-side transistor pair (S 0L , LS) to apply thereto the test-mode signal (V TM ) wherein the at least one of the high-side transistor pair (S 0H , HS) and the low-side transistor pair (S 0L , LS) is made selectively conductive or non-conductive based on the test-mode signal (V TM ).

公开(公告)号：EP4113840A1

公开(公告)日：2023-01-04

申请号：EP22180456.0

申请日：2022-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： D'ANGELO, Vittorio ,  CANNAVACCIUOLO, Salvatore ,  BENDOTTI, Valerio ,  SELVO, Paolo ,  ALAGNA, Diego

IPC: H03K17/18 ,  H03K17/689

Abstract: An isolated gate driver device (10) has: a low-voltage section (10a), having a control input (IN PWM ), which receives a PWM control signal (S PWM ) at a switching frequency (f PWM_HV ); a high-voltage section (10b), galvanically isolated from the low-voltage section, having a driving output (OUT DRV ), which provides a gate-driving signal (V G ), as a function of the PWM control signal, to a switch (18) of a power stage (14), and a feedback input (IN FB ), which receives at least one feedback signal (S FB ) indicative of the operation of the power stage; and a communication channel (15), which implements an isolated communication between the low-voltage and high-voltage sections. The high-voltage section comprises an ADC module (22), which converts the feedback signal into a digital data stream, and a conversion-control module (24), coupled to the ADC module for providing a conversion-trigger signal (S Trig ) that determines the start of conversion for acquisition of a new sample (S k ) of the feedback signal.

公开(公告)号：EP3575810B1

公开(公告)日：2020-08-05

申请号：EP19175888.7

申请日：2019-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： PENNISI, Orazio ,  BENDOTTI, Valerio ,  POLETTO, Vanni

IPC: G01R31/396