公开(公告)号：EP0887936A1

公开(公告)日：1998-12-30

申请号：EP97830295.8

申请日：1997-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Rigazio, Luca

IPC: H03L1/00 ,  H03K3/0231

CPC classification number: H03K3/2821 ,  H03K3/0231

Abstract: The controllable-frequency oscillator described is of the astable multivibrator type with two transistors (Q1, Q2) coupled to one another by means of a capacitor (C) and a positive-feedback circuit. In order to reduce the supply voltage of the oscillator to the minimum, the positive-feedback circuit is constituted by a differential amplifier (T3, T4, R3, R4 and G5).

Abstract translation: 所描述的可控频率振荡器是具有通过电容器（C）和正反馈电路彼此耦合的两个晶体管（Q1，Q2）的不稳定的多谐振荡器类型。 为了将振荡器的电源电压降至最低，正反馈电路由差分放大器（T3，T4，R3，R4和G5）构成。

公开(公告)号：EP0957584B1

公开(公告)日：2004-01-07

申请号：EP98830300.4

申请日：1998-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Ottini, Daniele

IPC: H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0896

公开(公告)号：EP0892499B1

公开(公告)日：2000-09-27

申请号：EP97830351.9

申请日：1997-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  De Micheli, Marco ,  Bruccoleri, Melchiorre ,  Rigazio, Luca

IPC: H03L7/07 ,  G11B20/10

CPC classification number: H03L7/07 ,  G11B20/1403

公开(公告)号：EP0957584A1

公开(公告)日：1999-11-17

申请号：EP98830300.4

申请日：1998-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Ottini, Daniele

IPC: H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0896

Abstract: A phase locked ring comprising a phase comparator, a charge pumping circuit, a loop filter and a voltage controlled oscillator, where the loop filter comprises two input terminals connected with two symmetric branches of the charge pumping circuit, each symmetric branch comprising a constant current generator and a pulsed current generator. Feedback paths are provided to control constant current generators through the voltage available on both loop filter terminals. According to the present invention, pulsed current generators (I7, I8) are separated from the respective loop filter terminals (N1 , N2) by circuit breaking switching means (S1, S2), said circuit breaking switching means (S1, S2) being controlled by phase signals (UP, DOWN) outputted from the phase comparator (2).

Abstract translation: 一种锁相环，包括相位比较器，电荷泵浦电路，环路滤波器和压控振荡器，其中环路滤波器包括与电荷泵浦电路的两个对称分支连接的两个输入端子，每个对称支路包括恒定电流发生器 和脉冲电流发生器。 提供反馈路径，通过两个环路滤波器端子上可用的电压来控制恒流发电机。 根据本发明，脉冲电流发生器（I7，I8）通过断路切换装置（S1，S2）与各个环路滤波器端子（N1，N2）分离，所述断路切换装置（S1，S2）被控制 通过从相位比较器（2）输出的相位信号（UP，DOWN）。

公开(公告)号：EP1093220B1

公开(公告)日：2004-12-29

申请号：EP99830653.4

申请日：1999-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Ranieri, Danilo ,  Brambilla, Davide ,  Botti, Edoardo ,  Celant, Luca

IPC: H03F1/52 ,  H04R3/00

CPC classification number: H03F1/52

公开(公告)号：EP0961269A1

公开(公告)日：1999-12-01

申请号：EP98830259.2

申请日：1998-04-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bollati, Giacomino ,  Bruccoleri, Melchiorre ,  Portaluri, Salvatore ,  Celant, Luca

IPC: G11B20/00 ,  G11B20/10 ,  G11B5/09

CPC classification number: G11B20/10046 ,  G11B2220/2516

Abstract: A method of equalizing a read channel of a mass memory device on a magnetic support, comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order comprised between 6 and 8 and a boost is implemented by introducing in the transfer function of the filter two real and opposed zeroes without altering the group delay.

Abstract translation: 一种均衡磁性支架上的大容量存储器件的读取通道的方法包括衰减来自电磁读取换能器的模拟信号的频谱的低频，而不会增加频谱的高频谐波分量。 模拟输入信号的频谱的低频通过包含在6和8之间的阶数的低通滤波器衰减，并且通过在滤波器的传递函数中引入两个实数和相对的零来实现升压，而不改变组延迟 。

公开(公告)号：EP1093220A1

公开(公告)日：2001-04-18

申请号：EP99830653.4

申请日：1999-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Ranieri, Danilo ,  Brambilla, Davide ,  Botti, Edoardo ,  Celant, Luca

IPC: H03F1/52 ,  H04R3/00

CPC classification number: H03F1/52

Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in

establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency;
sensing the rising edge of the timing pulse and setting a bistable circuit;
comparing the signal on the output nodes of the amplifiers channel with said window of permitted values;
resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values;
failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.

Abstract translation: 一种通过产生逻辑信号来估计放大信道的输出节点上的偏移的方法，该逻辑信号指示存在超过由负极限值定义的零电平对称的允许电平的窗口的电平的偏移，以及正的 限制值包括通过向检测电路的输入施加具有一定频率的定时脉冲来建立检测的间隔或相位; 感测定时脉冲的上升沿并设置双稳态电路; 将放大器通道的输出节点上的信号与允许值的窗口进行比较; 在所述初始设置之后，在所述允许值的窗口内的输出信号振幅发生时，重置所述双稳态电路; 所述双稳态电路的故障在检测阶段结束之前复位，发出过大的偏移。

公开(公告)号：EP0892499A1

公开(公告)日：1999-01-20

申请号：EP97830351.9

申请日：1997-07-14

Applicant: STMicroelectronics S.r.l.

Inventor： Celant, Luca ,  De Micheli, Marco ,  Bruccoleri, Melchiorre ,  Rigazio, Luca

IPC: H03L7/07 ,  G11B20/10

CPC classification number: H03L7/07 ,  G11B20/1403

Abstract: The integrated circuit described comprises two phase-locked loops (R-PLL, W-PLL) each with its own oscillator (OSC-1, OSC-2). To prevent locking owing to injection between the two oscillators due to stray currents in the integrated circuit, a noise generator (N-GEN) is coupled to the oscillator (OSC-2) of one of the loops (W-PLL) and means (TM) are provided for activating the noise generator (N-GEN) in a manner such that the noise injected changes the frequency of the oscillator (OSC-2) randomly when the other loop (R-PLL) is in operation.

Abstract translation: 集成电路描述由两锁相环（R-PLL，W-PLL）每个都有其自己的振荡器（OSC-1，OSC-2）。 为了防止由于两个振荡器之间的喷射由于在集成电路杂散电流锁定，噪声发生器（N-GEN）耦合到所述环中的一个（W-PLL）以及装置（的振荡器（OSC-2） TM）被提供用于激活噪声发生器（N-GEN）（以检查的方式做了噪声注入变化的振荡器OSC-2）随机地当其他环（R-PLL）是在操作中的频率。