Abstract:
In a logarithmic linear variable gain CMOS amplifier comprising a differential input pair of transistors with diode-connected load transistors, a second differential pair of transistors sharing the same diode-connected load transistors, a pair of current mirrors for programmably injecting respective bias currents in the common source modes of said two differential pairs of transistors, generated by a digital-to-analog converter, the groups delay is rendered independent from the gain and linearity inversely proportional to the gain by cross connnecting the control nodes of the second differential pair to the control nodes of the first differential input pair of transistors and by biasing the two differential pair of transistors such that the sum of their respecive bias current is maintained constant. Preferably, transistor means connected in parallel to each of said diode-connected load transitors are added for subtracting a constant amount of current from said sum current that would otherwise be flowing through the diode-connected load transistors.
Abstract:
A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.
Abstract:
A step gain-variable CMOS amplifier is based on the basic structure of a differential amplifier including an input pair of transistors (M1,M2), a bias current generator (M11) connected between a common source node of the input pair of transistors and the ground node of the circuit and a pair of load transistors (M9,M10) of same type of conductivity of the input pair connected between the supply voltage node and, respectively, to the drain nodes of the input transistors. The novel structure according to this invention comprises a plurality of either the input pairs of transistors (M3,M4,M5,M6,M7,M8) or of load pairs of transistors connectable in parallel for increasing the effective width of the resultant transistors. A plurality of path selection pairs of switches may be programmably closed for connecting in parallel the selected pairs of either input transisitors or of load transistors.
Abstract:
A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.
Abstract:
An AC differential amplifier comprises a pair of identical differential transconductance stages (TA1,TA2) the corresponding output nodes of which (OUTA,OUTB), connected in common and constituting a pair of output nodes of the AC differential amplifier, are connected to a supply line (VCC) through respective load resistors (R2), an input node of one transconductance stage being coupled through capacitive means to an input node of the other transconductance stage, the other input nodes (INA,INB) of the two transconductance stages (TA1,TA2) constituting the input terminals of the amplifier.
Abstract:
A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current ( iz ), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current ( iz ) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.
Abstract:
A BiCMOS ECL/CMOS interface circuit for converting a high frequency pseudo-ECL signal with a voltage swing in the order of few hundreds of millivolts into a CMOS signal with a voltage swing substantially equal to the supply voltage, comprising a differential input stage composed of a pair of NPN bipolar junction transistors (Q1, Q2) in a common emitter configuration, a bias current generator (IBIAS) functionally coupled between the common emitter node of said NPN transistors and ground and means driven by a respective transistor of said input pair (Q1, Q2) driving the control node of a respective output CMOS stage (M5-M7, M6-M8), is provided with first and second common-collector stages each constituted by an NPN bipolar junction transistor(Q3, Q4) and driven by a respective transistor of said pair of NPN transistors (Q1, Q2); and with a pair of identical PMOS transistors (M1, M2) with gates connected in common to a bias voltage (POL), each PMOS transistor (M1, M2) having a source coupled to the emitter of a respective transistor (Q3, Q4) of said common-collector stages and a drain connected to a load current generator (I) and to said control node of a respective output CMOS stage (M5-M7, M6-M8), for reducing current absorption without impairing performance.