公开(公告)号：EP1014573B1

公开(公告)日：2004-07-14

申请号：EP98830760.9

申请日：1998-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Bollati, Giacomino ,  Alini, Roberto ,  Ottini, Daniele ,  Bruccoleri, Melchiorre

IPC: H03H11/04

CPC classification number: H03H11/0422

公开(公告)号：EP1513252A1

公开(公告)日：2005-03-09

申请号：EP03425568.7

申请日：2003-09-02

Applicant: STMicroelectronics S.r.l.

Inventor： Gaeta, Marco ,  Bollati, Giacomino ,  Bongiorni, Marco

IPC: H03G7/00 ,  H03G7/06

CPC classification number: H03G7/06 ,  H03G7/001

Abstract: In a logarithmic linear variable gain CMOS amplifier comprising a differential input pair of transistors with diode-connected load transistors, a second differential pair of transistors sharing the same diode-connected load transistors, a pair of current mirrors for programmably injecting respective bias currents in the common source modes of said two differential pairs of transistors, generated by a digital-to-analog converter, the groups delay is rendered independent from the gain and linearity inversely proportional to the gain by cross connnecting the control nodes of the second differential pair to the control nodes of the first differential input pair of transistors and by biasing the two differential pair of transistors such that the sum of their respecive bias current is maintained constant.
Preferably, transistor means connected in parallel to each of said diode-connected load transitors are added for subtracting a constant amount of current from said sum current that would otherwise be flowing through the diode-connected load transistors.

Abstract translation: 在包括具有二极管连接的负载晶体管的差分输入对晶体管的对数线性可变增益CMOS放大器中，共享相同二极管连接的负载晶体管的第二差分对晶体管，一对电流镜，用于可编程地将相应的偏置电流注入到 由数模转换器产生的所述两个差分对晶体管的共模源，通过将第二差分对的控制节点与第二差分对的交叉连接相互连接，使组延迟独立于与增益成反比的增益和线性度 控制第一差分输入对晶体管的节点，并通过偏置两个差分对的晶体管，使得它们相应的偏置电流之和保持恒定。 添加并联连接到每个所述二极管连接的负载转换器的晶体管装置，用于从否则将流过二极管连接的负载晶体管的所述和电流中减去恒定量的电流。

公开(公告)号：EP1005170B1

公开(公告)日：2002-02-13

申请号：EP98830712.0

申请日：1998-11-27

Applicant: STMicroelectronics S.r.l.

Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Bollati, Giacomino ,  Demicheli, Marco

IPC: H03M1/36 ,  H03M7/16

CPC classification number: H03M1/0809 ,  H03M1/365

公开(公告)号：EP1020990A2

公开(公告)日：2000-07-19

申请号：EP99830379.6

申请日：1999-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

IPC: H03F3/45

CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

Abstract translation: 一种跨导体，包括由一对输入晶体管组成的差分级，与所述差分级的输入晶体管的源极对流的电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应的输入晶体管的源极和 公共接地节点具有由串联的一个或多个晶体管组成的退化电阻线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设计成在三极管中工作 地区。

公开(公告)号：EP1515431A1

公开(公告)日：2005-03-16

申请号：EP03425589.3

申请日：2003-09-11

Applicant: STMicroelectronics S.r.l.

Inventor： Gaeta, Marco ,  Bollati, Giacomino

IPC: H03F1/32 ,  H03F3/45 ,  H03G3/30

CPC classification number: H03F3/45183 ,  H03F1/3211 ,  H03F3/45623 ,  H03G1/0088

Abstract: A step gain-variable CMOS amplifier is based on the basic structure of a differential amplifier including an input pair of transistors (M1,M2), a bias current generator (M11) connected between a common source node of the input pair of transistors and the ground node of the circuit and a pair of load transistors (M9,M10) of same type of conductivity of the input pair connected between the supply voltage node and, respectively, to the drain nodes of the input transistors. The novel structure according to this invention comprises a plurality of either the input pairs of transistors (M3,M4,M5,M6,M7,M8) or of load pairs of transistors connectable in parallel for increasing the effective width of the resultant transistors. A plurality of path selection pairs of switches may be programmably closed for connecting in parallel the selected pairs of either input transisitors or of load transistors.

Abstract translation: 步进增益CMOS放大器基于差分放大器的基本结构，该差分放大器包括输入一对晶体管（M1，M2），连接在输入晶体管对的公共源极之间的偏置电流发生器（M11）和 接地节点和连接在电源电压节点和输入晶体管的漏极节点之间的输入对具有相同类型导电性的一对负载晶体管（M9，M10）。 根据本发明的新颖结构包括多个晶体管（M3，M4，M5，M6，M7，M8）的输入对或者可并联连接的晶体管的负载对，以增加所得晶体管的有效宽度。 多个路径选择对开关可以可编程地闭合，用于并联连接所选择的输入通道或负载晶体管对。

公开(公告)号：EP1014362B1

公开(公告)日：2003-11-19

申请号：EP98830756.7

申请日：1998-12-15

Applicant: STMicroelectronics S.r.l.

Inventor： Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Malfa, Maurizio ,  Bollati, Giacomino

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B5/012 ,  G11B5/09

公开(公告)号：EP1020990A3

公开(公告)日：2000-08-02

申请号：EP99830379.6

申请日：1999-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stefano ,  Bollati, Giacomino ,  Malfa, Maurizio ,  Savo, Pierandrea

IPC: H03F3/45

CPC classification number: H03F3/45632 ,  H03F3/45197 ,  H03F2203/45466

Abstract: A transconductor comprising a differential stage composed of a pair of input transistors, a resistive line of degeneration convecting the sources of the input transistors of said differential stage, a pair of bias current generators, each coupled between the source of a respective input transistor and a common ground node, has said resistive line of degeneration composed of one or more transistors in series, the gate of which is coupled to a voltage at least equal to the common mode voltage of the differential stage, and which are sized to operate in the triode region.

Abstract translation: 一种跨导器，包括由一对输入晶体管构成的差分级，一个对所述差分级的输入晶体管的源极进行对流的负反馈电阻线，一对偏置电流发生器，每个偏置电流发生器耦合在相应输入晶体管的源极和 共同的接地节点具有由串联的一个或多个晶体管构成的电阻性退化线，其栅极耦合到至少等于差分级的共模电压的电压，并且其尺寸被设定为在三极管 地区。

公开(公告)号：EP1511170A1

公开(公告)日：2005-03-02

申请号：EP03425561.2

申请日：2003-08-28

Applicant: STMicroelectronics S.r.l.

Inventor： Bollati, Giacomino

IPC: H03F1/08 ,  H03F3/45 ,  H03F1/26

CPC classification number: H03F3/45085 ,  H03F1/083 ,  H03F1/26 ,  H03F1/48 ,  H03F3/4508 ,  H03F3/45475 ,  H03F3/45484 ,  H03F2200/36 ,  H03F2200/372 ,  H03F2203/45111 ,  H03F2203/45138 ,  H03F2203/45548 ,  H03F2203/45702

Abstract: An AC differential amplifier comprises a pair of identical differential transconductance stages (TA1,TA2) the corresponding output nodes of which (OUTA,OUTB), connected in common and constituting a pair of output nodes of the AC differential amplifier, are connected to a supply line (VCC) through respective load resistors (R2), an input node of one transconductance stage being coupled through capacitive means to an input node of the other transconductance stage, the other input nodes (INA,INB) of the two transconductance stages (TA1,TA2) constituting the input terminals of the amplifier.

Abstract translation: AC差分放大器包括一对相同的差分跨导级（TA1，TA2），其相应的输出节点（OUTA，OUTB）被连接在一起并构成一对AC差动放大器的输出节点，连接到电源 线路（VCC）通过相应的负载电阻（R2），一个跨导级的输入节点通过电容性装置耦合到另一跨导级的输入节点，两个跨导级（TA1）的其他输入节点（INA，INB） ，TA2）构成放大器的输入端。

公开(公告)号：EP1014573A1

公开(公告)日：2000-06-28

申请号：EP98830760.9

申请日：1998-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Bollati, Giacomino ,  Alini, Roberto ,  Ottini, Daniele ,  Bruccoleri, Melchiorre

IPC: H03H11/04

CPC classification number: H03H11/0422

Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current ( iz ), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current ( iz ) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.

Abstract translation: 具有可编程均衡的低通滤波器，其包括至少一个二次电池（BIQUAD）和与输入电压的导数成比例的电流（iz）中的输入电压（Vin）的转换器，其被注入到 为了在滤波器的传递函数中引入两个实数和相对的零点，双级电容（BIQUAD）由两个结构相似的电路组成，功能上串联连接，每个电路由一个二次电池和一个具有两个输出的输入级组成 通过第一电流输出（A），通过在所述两个电路中的第一个中的直接耦合并且在所述两个电路中的第二个中以反向方式，在相应的二次电池的输入电容器（C1）上注入所述电流（iz） ; 第二电压输出（B）耦合到相应的双二次电池的输入端。

公开(公告)号：EP1006658A1

公开(公告)日：2000-06-07

申请号：EP98830727.8

申请日：1998-12-03

Applicant: STMicroelectronics S.r.l.

Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Marchese, Stefano ,  Bollati, Giacomino

IPC: H03K19/0175

CPC classification number: H03K19/017527

Abstract: A BiCMOS ECL/CMOS interface circuit for converting a high frequency pseudo-ECL signal with a voltage swing in the order of few hundreds of millivolts into a CMOS signal with a voltage swing substantially equal to the supply voltage, comprising a differential input stage composed of a pair of NPN bipolar junction transistors (Q1, Q2) in a common emitter configuration, a bias current generator (IBIAS) functionally coupled between the common emitter node of said NPN transistors and ground and means driven by a respective transistor of said input pair (Q1, Q2) driving the control node of a respective output CMOS stage (M5-M7, M6-M8), is provided with first and second common-collector stages each constituted by an NPN bipolar junction transistor(Q3, Q4) and driven by a respective transistor of said pair of NPN transistors (Q1, Q2); and with a pair of identical PMOS transistors (M1, M2) with gates connected in common to a bias voltage (POL), each PMOS transistor (M1, M2) having a source coupled to the emitter of a respective transistor (Q3, Q4) of said common-collector stages and a drain connected to a load current generator (I) and to said control node of a respective output CMOS stage (M5-M7, M6-M8), for reducing current absorption without impairing performance.

Abstract translation: 一种BiCMOS ECL / CMOS接口电路，用于将具有几百毫伏数量级的电压摆幅的高频伪ECL信号转换成具有基本上等于电源电压的电压摆幅的CMOS信号，包括差分输入级，其由 一个共同的发射结构的一对NPN双极结晶体管（Q1，Q2），功能上耦合在所述NPN晶体管的公共发射极节点与地之间的偏置电流发生器（IBIAS）和由所述输入对的相应晶体管驱动的装置 Q1，Q2）驱动各个输出CMOS级（M5-M7，M6-M8）的控制节点，设置有由NPN双极结型晶体管（Q3，Q4）构成的第一和第二公共集电极级，并由 所述一对NPN晶体管（Q1，Q2）的相应晶体管; 并且通过一对具有与偏置电压（POL）共同连接的栅极的一对相同的PMOS晶体管（M1，M2），每个PMOS晶体管（M1，M2）具有耦合到相应晶体管（Q3，Q4）的发射极的源极， 的所述共集电极级和连接到负载电流发生器（I）的漏极以及相应的输出CMOS级（M5-M7，M6-M8）的所述控制节点，用于减小电流吸收而不损害性能。