公开(公告)号：EP1696485A1

公开(公告)日：2006-08-30

申请号：EP05425096.4

申请日：2005-02-24

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore ,  Modica, Roberto

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/316

CPC classification number: H01L23/544 ,  H01L21/32 ,  H01L21/76286 ,  H01L21/8222 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/8249 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7824 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: Process for manufacturing an electronic semiconductor device, wherein a SOI wafer (20) is provided, formed by a bottom layer (21) of semiconductor material, an insulating layer (22), and a top layer (50) of semiconductor material, stacked on top of one another; alignment marks (32) are formed in the top layer; an implanted buried region (30) is formed, aligned to the alignment marks; a hard mask (52,53) is formed on top of the top layer (23;50) so as to align it to the alignment marks (32); using the hard mask, the top layer (23;50) is selectively removed so as to form a trench (55) extending up to the insulating layer (22); there a lateral-insulation region (60) in the trench (55), that is contiguous to the insulating layer (22) and delimits with the latter an insulated well (61) of semiconductor material; and electronic components (65-76) are formed in the top layer (23;50).

Abstract translation: 用于制造电子半导体器件，worin一个SOI晶片（20）的过程被提供，由半导体材料的上绝缘层（22）的底层（21），和半导体材料的顶层（50），层叠形成 彼此的顶部上; 对准标记（32）形成在所述顶层; 注入掩埋区（30）形成，对准的对准标记; 硬掩模（52,53）形成在所述顶层（23; 50）的顶部上，以便将其对准的对准标记（32）; 使用硬掩模，顶部层（23; 50）被选择性地去除以形成沟槽（55）一直延伸到绝缘层（22）; 在（55）有一横向绝缘区域（60）的沟槽所做的是邻接于绝缘层（22），并用绝缘良好的（61）的半导体材料的后界定; 和电子部件（65-76）形成在所述顶层（23; 50）。