公开(公告)号：EP1798799B1

公开(公告)日：2008-09-24

申请号：EP05425892.6

申请日：2005-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Siciliano, Simone Angelo ,  La Magna, Luigi ,  Leonardi, Salvatore

IPC: H01M8/10 ,  H01M8/24 ,  B81C1/00 ,  B81B7/02

CPC classification number: H01M8/1097 ,  H01M8/0271 ,  H01M8/04089 ,  H01M8/241 ,  H01M8/2425 ,  H01M2008/1095

Abstract: A planarly integrated fuel cell structure, formed in a region (2) preliminarily rendered pervious to fluid flow and electrically nonconductive of the monocrystalline silicon substrate (1), has at least a pair of parallel channels, an anode feed channel (3) and a cathode feed channel (4), respectively, extending in the oxidized porous oxidized silicon region and defining a central oxidized porous silicon ridge (5) therebetween; a dielectric cap (B, P, 6b, 17) over said channelled oxidized porous silicon region (2), having at least an inlet and an outlet hole (11-12, 13-14) formed therethrough in correspondence of one end and the opposite end, respectively, of each one of the parallel channels (3, 4) underneath, for separately circulating a fluid fuel in the anode channel (3) and air or other oxygen containing mixture in the cathode channel (4); a pair of parallel spaced solid metal cell electrodes (7, 8) extending over the top surface of said central oxidized porous silicon ridge (5) defined between said parallel channels (3, 4), for the whole length of the channels; cathodically deposited uninterrupted electrically conductive threads (7', 8') of a catalytic metal, stemming from a bottom surface of each of said solid metal cell electrodes (7, 8) and extending to the side face of said central ridge (5) of oxidized porous silicon constituting a side wall of the channel (3, 4) extending alongside of the electrode (7, 8); ion permeable resin filling the pores of the nonconductive porous silicon in the innermost central portion of the ridge (5) to impede fluid flow from one channel (3) to the other (4), and only partly filling the pores in proximity of the definition sides of said central ridge (5) constituting side walls of one and of the other of said parallel channels (3, 4), forming uninterrupted ion permeable resin domains extending from catalytic metal threads (7') stemming from one solid metal cell electrode (7) to catalytic metal threads (8') stemming from the other solid metal cell electrode (8); and means for electrically connecting said two parallel solid metal cell electrodes (7, 8) to a load circuit of the cell.

公开(公告)号：EP0996158B9

公开(公告)日：2008-06-18

申请号：EP98830638.7

申请日：1998-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L27/08

CPC classification number: H01L21/76208 ,  H01L21/761 ,  H01L27/0802

公开(公告)号：EP0996158B1

公开(公告)日：2007-09-12

申请号：EP98830638.7

申请日：1998-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L27/08

CPC classification number: H01L21/76208 ,  H01L21/761 ,  H01L27/0802

公开(公告)号：EP1302984A1

公开(公告)日：2003-04-16

申请号：EP01830639.9

申请日：2001-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L27/02 ,  H01L21/762

CPC classification number: H01L29/74 ,  H01L21/76264 ,  H01L27/0255 ,  H01L27/1203

Abstract: A protection structure against electrostatic discharges (ESD) for a semiconductor electronic device (20) that is integrated inside a well (2) is disclosed, wherein the well (2) is formed on a SOI substrate (3) and isolated dielectrically by a buried oxide layer (4) and an isolation structure, which isolation structure includes in turn at least a dielectric trench (7) filled with a filler material (8).
Advantageously according to the invention, the protection structure (21) is formed at the isolation structure.

Abstract translation: 对用于半导体电子装置的静电放电（ESD）的保护结构（20）没有被集成在井（2）内是圆盘游离缺失，worin阱（2）上形成SOI衬底（3）和介电隔离通过掩埋 氧化物层（4）和在隔离结构，其包括隔离结构反过来至少一个介电沟槽（7），填充有填充材料（8）。 有利地gemäß到本发明，该保护结构（21）在所述隔离结构形成。

公开(公告)号：EP1037274A2

公开(公告)日：2000-09-20

申请号：EP99830531.2

申请日：1999-08-26

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L21/762 ,  H01L27/06

CPC classification number: H01L21/761 ,  H01L21/76208 ,  H01L27/088

Abstract: The invention relates to an electronic power device, being integrated monolithically in a semiconductor substrate (1) and having at least a first power region (HV) and at least a second region (LV), each region comprising at least one P/N junction consisting of a first semiconductor region (3) with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region (2) with the opposite conductivity from the first, and including at least one interface structure between the two regions (HV,LV), of substantial thickness and limited planar size, comprising at least one trench (12) filled with dielectric material.
The invention further relates to a method of manufacturing an electronic power device being monolithically integrated in a semiconductor substrate (1) and having a first power region (HV) and at least a second region (LV), each said region comprising at least one P/N junction formed of a first semiconductor region (3) with a first type of conductivity, extending through the substrate from the top surface of the device and being diffused into a second semiconductor region (2) with the opposite conductivity from the first, a silicon oxide-filled trench being formed by the following steps:

forming, in the substrate, a plurality of small trenches (10) having predetermined widths and being delimited by a corresponding plurality of semiconductor material walls (11) having second predetermined widths;
oxidising the semiconductor by a thermal process directed to oxidise the walls (11) and produce a single trench (12).

Abstract translation: 本发明涉及在电子功率器件，被在半导体基板单片集成（1）和具有至少一个第一电力区域（HV）和至少一个第二区（LV），每个区域包括至少一个P / N结 的第一半导体区域（3）的具有第一类型导电性的，其中第一半导体区通过将基底从所述装置的顶部表面延伸，并扩散到与相反导电性的第二半导体区域（2）从所述第一组成， 包括和相当大的厚度和有限的平面尺寸的两个区域（HV，LV）之间的至少一个接口结构，其包括填充有电介质材料的至少一个沟槽（12）。 基板本发明还涉及到制造电子功率器件的方法被单片集成在一个半导体（1），并具有第一功率区（HV）和至少一个第二区（LV），每个所述区域包括至少一个P / N结形成用第一导电类型的第一半导体区域（3），通过将基底从所述器件的顶表面延伸，并扩散到第二半导体区（2）与相反导电从第一，一个 氧化物填充硅槽的形成通过下述步骤：形成在衬底中，具有预定的宽度和由半导体材料的壁的相应的多个（11）界定具有第二预定宽度的小沟槽的多个（10）; 氧化通过热工序中的半导体涉及氧化的壁（11）和产生单个沟槽（12）。

公开(公告)号：EP1032031A2

公开(公告)日：2000-08-30

申请号：EP99830532.0

申请日：1999-08-26

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L21/762 ,  H01L27/06

CPC classification number: H01L29/0653 ,  H01L21/761 ,  H01L21/76208 ,  H01L27/0611 ,  H01L29/0661

Abstract: The invention relates to an electronic power device integrated monolithically in a semiconductor substrate (1), including at least one power region, itself having at least one P/N junction provided therein which comprises a first semiconductor region (3) with a first type of conductivity extending into the substrate from the top surface of the device and being diffused into a second semiconductor region (2) with the opposite conductivity from the first, and including at least one edge protection structure of substantial thickness and limited planar size incorporating at least one trench (10) filled with dielectric material.
The invention further relates to a method of manufacturing an electronic power device integrated monolithically in a semiconductor substrate (1), including at least one transistor having at least one P/N junction provided therein which comprises a first semiconductor region (3) with a first type of conductivity extending into the substrate from the top surface of the device and being diffused into a second semiconductor region (2) with the opposite conductivity from the first, and a silicon oxide trench (10), provided as an edge protection structure, which is formed by the following steps:

forming a plurality of small trenches (8) in the substrate which have predetermined lengths and are bounded by a plurality of corresponding walls (9) of semiconductor material having predetermined widths;
oxidising the semiconductor by means of a thermal process in order to oxidise the walls (9) and produce the oxide trench (10).

Abstract translation: 本发明涉及一种在在半导体基片（1）包括至少一个功率区域中，本身具有其中设置至少一个P / N结，其包括第一半导体区域单片集成电子电源装置（3）与第一类型的 电导率延伸到从装置的顶部表面上的衬底和扩散到与从第一相反导电性的第二半导体区域（2），并且包括在相当大的厚度和有限的平面尺寸的至少一个边缘保护结构中结合至少一种 沟槽（10）填充有电介质材料。 本发明还涉及到在半导体衬底（1）包括其中提供了一种具有至少一个P / N结的至少一个晶体管，其中（3）与第一包含第一半导体区域单片集成制造电子功率器件的方法 导电性类型扩展成将基底从所述装置的顶部表面和扩散到第二半导体区（2）与来自第一对置的导电性，和氧化硅的沟槽（10），作为提供给边缘保护结构，其 是通过以下步骤形成的：在具有预定的长度和由对应的具有预定宽度的半导体材料（9）的墙壁的多元性是有界的该衬底上形成的小沟槽（8）的多元性; 氧化通过热处理的方式的半导体，以氧化所述壁（9）和产生的氧化物沟槽（10）。

公开(公告)号：EP0996158A1

公开(公告)日：2000-04-26

申请号：EP98830638.7

申请日：1998-10-23

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L27/08

CPC classification number: H01L21/76208 ,  H01L21/761 ,  H01L27/0802

Abstract: Resistive structure (10) integrated on a semiconductive substrate (1) having a first type of conductivity and formed by a serpentine region (2) of conductivity which is opposite to that of the semiconductive substrate in which at least two parallel portions (3) of the serpentine region (2) there is at least one insulating trench.

Abstract translation: 电阻结构（10）集成在具有第一类型导电性的半导体衬底（1）上，并由与半导体衬底的至少两个平行部分（3）相反的导电性的蛇形区域（2）形成， 蛇形区域（2）中至少有一个绝缘沟槽。

公开(公告)号：EP0966042B1

公开(公告)日：2008-01-09

申请号：EP98830373.1

申请日：1998-06-19

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L27/07 ,  H01L27/06

CPC classification number: H01L27/0716 ,  H01L27/0635 ,  H01L29/7302 ,  H01L29/739 ,  H01L29/7803 ,  H01L29/7808

公开(公告)号：EP1742251A1

公开(公告)日：2007-01-10

申请号：EP05425477.6

申请日：2005-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore ,  Caligiore, Claudia

IPC: H01L21/20 ,  H01L21/336

CPC classification number: H01L21/02686 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1281 ,  H01L29/66757

Abstract: In a process for manufacturing a thin-film transistor device the following steps are envisaged: forming a dielectric insulation layer (16) on a substrate (15); forming an amorphous silicon layer (17) on the dielectric insulation layer (16); crystallizing the amorphous silicon layer (17), so as to obtain polycrystalline silicon (19); forming gate structures (18b; 20, 24) on the polycrystalline silicon (19); and forming first doped regions (27-30) within the polycrystalline silicon (19) laterally with respect to the gate structures (18b; 20, 24). During the crystallizing step, the following steps are envisaged: forming first capping dielectric regions (18a) on the amorphous silicon layer (17); and then irradiating the amorphous silicon layer (17) using a laser so as to form active areas (19) of polycrystalline silicon separated by separation portions (17a) of amorphous silicon underlying the first capping dielectric regions (18a).

Abstract translation: 在制造薄膜晶体管器件的工艺中，设想以下步骤：在衬底（15）上形成绝缘层（16）; 在绝缘层（16）上形成非晶硅层（17）; 使非晶硅层（17）结晶，得到多晶硅（19）; 在多晶硅（19）上形成栅极结构（18b; 20,24）; 以及在所述多晶硅（19）内相对于所述栅极结构（18b; 20,24）横向形成第一掺杂区域（27-30）。 在结晶步骤中，设想以下步骤：在非晶硅层（17）上形成第一封盖介电区（18a）; 然后使用激光照射非晶硅层（17），以形成由第一覆盖电介质区域（18a）下面的非晶硅的分离部分（17a）分离的多晶硅的有源区域（19）。

公开(公告)号：EP0756329B1

公开(公告)日：2002-01-16

申请号：EP95830328.1

申请日：1995-07-27

Applicant: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe ,  STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore ,  Lizzio, Pietro ,  Patti, Davide Giuseppe ,  Palara, Sergio

IPC: H01L29/732 ,  H01L29/10 ,  H01L21/331

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/7322