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    Time interleaved digital signal processing in a read channel with reduced noise figure
    4.
    发明公开
    Time interleaved digital signal processing in a read channel with reduced noise figure 有权
    Zeitverschachteltes digitales Signalverarbeitungsverfahren在einem Lesekanal mit reduziertem Rauschmass

    公开(公告)号：EP1006525A1

    公开(公告)日：2000-06-07

    申请号：EP98830718.7

    申请日：1998-12-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bruccoleri, Melchiorre ,  Demicheli, Marco ,  Ottini, Daniele ,  Savo, Alessandro

    IPC: G11B20/00

    CPC classification number: G11B20/10277 ,  G11B20/10509

    Abstract: A read and analog-to-digital data conversion channel comprising preamplifying circuits (Pre-Amp), automatic gain control circuits (VGA), harmonics filters (MRA), equalizing low pass filters (LPF), a time interleaved analog-to-digital converter (INTERLEAVED ATOD) including a pair of identical analog/digital converters (ATOD_EVEN, ATOD_ODD) functioning in parallel and at a half clock frequency, subdividing the signal path into two parallel paths through said two identical converters, one for even bits and the other for odd bits, and a digital post-processing block (DIGITAL Post Processing) fed by two output streams of said time interleaved converter (INTERLEAVED ATOD) and outputting a reconstructed data stream (DATA) and controlling said circuits, through dedicated digital-to-analog converters (DAC_VGA, DAC_MRA, DAC_FC, DAC_BOOST), means for compensating the offset of the digital-to-analog converters contained in said pair of identical analog-to-digital converters (ATOD_EVEN, ATOD_ODD) of said time interleaved converter (INTERLEAVED ATOD), controlled by said post-processing block (DIGITAL Post Processing) through a digital-to-analog converter, further comprises two distinct offset compensating circuits, each composed of an offset compensating stage (OFFSET_EVEN_STAGE, OFFSET_ODD_STAGE) independently controlled by said digital post-processing block through a dedicated digital-to-analog converter (DAC_OFF_E, DAC_OFF_O), preventing appearance of spurious patterns in frequency domain.

    Abstract translation: 读和模数转换通道，包括前置放大电路（Pre-Amp），自动增益控制电路（VGA），谐波滤波器（MRA），均衡低通滤波器（LPF），时间交错模数转换 转换器（INTERLEAVED ATOD）包括一对并行和半个时钟频率工作的一对相同的模拟/数字转换器（ATOD_EVEN，ATOD_ODD），将信号路径细分为通过所述两个相同转换器的两个并行路径，一个用于偶数位，另一个用于偶数位 以及由所述时间交织转换器（INTERLEAVED ATOD）的两个输出流馈送的数字后处理块（DIGITAL Post Processing），并输出重构数据流（DATA）并通过专用数字 - 模拟转换器（DAC_VGA，DAC_MRA，DAC_FC，DAC_BOOST），用于补偿包含在所述相同模数转换器对（ATOD_EVEN，ATOD_ODD）中的数/模转换器的偏移量的装置 由所述后处理块（DIGITAL后处理）通过数模转换器控制的所述时间交织转换器（INTERLEAVED ATOD）还包括两个不同的偏移补偿电路，每个偏移补偿电路由偏移补偿级（OFFSET_EVEN_STAGE，OFFSET_ODD_STAGE ）通过专用数模转换器（DAC_OFF_E，DAC_OFF_O）独立地由所述数字后处理块控制，从而防止在频域中出现杂散模式。

    Flash analog-to-digital converter
    7.
    发明公开
    Flash analog-to-digital converter 有权
    闪光模拟数字电视

    公开(公告)号：EP1005170A1

    公开(公告)日：2000-05-31

    申请号：EP98830712.0

    申请日：1998-11-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Bollati, Giacomino ,  Demicheli, Marco

    IPC: H03M1/36 ,  H03M7/16

    CPC classification number: H03M1/0809 ,  H03M1/365

    Abstract: A flash analog-to-digital converter comprising a bank of comparators (COMPi) with a differential output, generating a thermometric code and a bank of three-input (A,B,C) logic NOR gates (NORj) for correcting errors in said thermometric code, has enhanced immunity to noise and reduced imprecisions, especially at high conversion rates upon occurence of metastability within the comparators, by providing for a passive interface constituted by a plurality of voltage dividers (Ra-Rb), each connected between the noninverted output (out_p) of a respective comparator (COMPi) and the inverted output (out_n) of the comparator of higher order (COMPi+1) of said bank; a corresponding logic NOR gate (NORj) of said bank having a first input (A) coupled to the inverted output (out_n) of said respective comparator (COMPi-1), a second input (B) coupled to the noninverted output (out_p) of said comparator (COMPi) of higher order and a third input (C) coupled to an intermediate tap of said voltage divider (Ra-Rb).

    Abstract translation: 一种闪存模数转换器，包括具有差分输出的一组比较器（COMPi），产生一个温度测量代码和一组三输入（A，B，C）逻辑或非门（NORj），用于校正所述 通过提供由多个分压器（Ra-Rb）构成的无源接口，每个连接在非反相输出端（Ra-Rb）之间，具有增强的抗噪声能力和减小的不精确性，特别是在比较器内发生亚稳态时的高转换速率 （COMPi）和所述存储体的高阶比较器（COMPi + 1）的反相输出（out_n）的输出（out_p） 所述存储体的对应逻辑或非门（NORj）具有耦合到所述各个比较器（COMPi-1）的反相输出（out_n）的第一输入（A），耦合到非反相输出（out_p）的第二输入（B） 的比较器（COMPi）和耦合到所述分压器（Ra-Rb）的中间抽头的第三输入端（C）。

    Analog equalization low pass filter structure
    8.
    发明公开
    Analog equalization low pass filter structure 有权
    Tiefpassfilterstruktur mit analoger Entzerrung

    公开(公告)号：EP1014573A1

    公开(公告)日：2000-06-28

    申请号：EP98830760.9

    申请日：1998-12-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bollati, Giacomino ,  Alini, Roberto ,  Ottini, Daniele ,  Bruccoleri, Melchiorre

    IPC: H03H11/04

    CPC classification number: H03H11/0422

    Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current ( iz ), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current ( iz ) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.

    Abstract translation: 具有可编程均衡的低通滤波器，其包括至少一个二次电池（BIQUAD）和与输入电压的导数成比例的电流（iz）中的输入电压（Vin）的转换器，其被注入到 为了在滤波器的传递函数中引入两个实数和相对的零点，双级电容（BIQUAD）由两个结构相似的电路组成，功能上串联连接，每个电路由一个二次电池和一个具有两个输出的输入级组成 通过第一电流输出（A），通过在所述两个电路中的第一个中的直接耦合并且在所述两个电路中的第二个中以反向方式，在相应的二次电池的输入电容器（C1）上注入所述电流（iz） ; 第二电压输出（B）耦合到相应的双二次电池的输入端。

    Low dissipation biCMOS ECL/CMOS interface
    9.
    发明公开
    Low dissipation biCMOS ECL/CMOS interface 审中-公开
    Bi CMOS CMOS ECL / CMOS Schnittstelle mit Niedrigem Verbrauch

    公开(公告)号：EP1006658A1

    公开(公告)日：2000-06-07

    申请号：EP98830727.8

    申请日：1998-12-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ottini, Daniele ,  Bruccoleri, Melchiorre ,  Marchese, Stefano ,  Bollati, Giacomino

    IPC: H03K19/0175

    CPC classification number: H03K19/017527

    Abstract: A BiCMOS ECL/CMOS interface circuit for converting a high frequency pseudo-ECL signal with a voltage swing in the order of few hundreds of millivolts into a CMOS signal with a voltage swing substantially equal to the supply voltage, comprising a differential input stage composed of a pair of NPN bipolar junction transistors (Q1, Q2) in a common emitter configuration, a bias current generator (IBIAS) functionally coupled between the common emitter node of said NPN transistors and ground and means driven by a respective transistor of said input pair (Q1, Q2) driving the control node of a respective output CMOS stage (M5-M7, M6-M8), is provided with first and second common-collector stages each constituted by an NPN bipolar junction transistor(Q3, Q4) and driven by a respective transistor of said pair of NPN transistors (Q1, Q2); and with a pair of identical PMOS transistors (M1, M2) with gates connected in common to a bias voltage (POL), each PMOS transistor (M1, M2) having a source coupled to the emitter of a respective transistor (Q3, Q4) of said common-collector stages and a drain connected to a load current generator (I) and to said control node of a respective output CMOS stage (M5-M7, M6-M8), for reducing current absorption without impairing performance.

    Abstract translation: 一种BiCMOS ECL / CMOS接口电路，用于将具有几百毫伏数量级的电压摆幅的高频伪ECL信号转换成具有基本上等于电源电压的电压摆幅的CMOS信号，包括差分输入级，其由 一个共同的发射结构的一对NPN双极结晶体管（Q1，Q2），功能上耦合在所述NPN晶体管的公共发射极节点与地之间的偏置电流发生器（IBIAS）和由所述输入对的相应晶体管驱动的装置 Q1，Q2）驱动各个输出CMOS级（M5-M7，M6-M8）的控制节点，设置有由NPN双极结型晶体管（Q3，Q4）构成的第一和第二公共集电极级，并由 所述一对NPN晶体管（Q1，Q2）的相应晶体管; 并且通过一对具有与偏置电压（POL）共同连接的栅极的一对相同的PMOS晶体管（M1，M2），每个PMOS晶体管（M1，M2）具有耦合到相应晶体管（Q3，Q4）的发射极的源极， 的所述共集电极级和连接到负载电流发生器（I）的漏极以及相应的输出CMOS级（M5-M7，M6-M8）的所述控制节点，用于减小电流吸收而不损害性能。

    Phase locked loop circuit and control method thereof
    10.
    发明公开
    Phase locked loop circuit and control method thereof 失效
    Phasenregelschleife und Verfahren zu deren Steuerung

    公开(公告)号：EP0957584A1

    公开(公告)日：1999-11-17

    申请号：EP98830300.4

    申请日：1998-05-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Celant, Luca ,  Demicheli, Marco ,  Bruccoleri, Melchiorre ,  Ottini, Daniele

    IPC: H03L7/089

    CPC classification number: H03L7/0893 ,  H03L7/0896

    Abstract: A phase locked ring comprising a phase comparator, a charge pumping circuit, a loop filter and a voltage controlled oscillator, where the loop filter comprises two input terminals connected with two symmetric branches of the charge pumping circuit, each symmetric branch comprising a constant current generator and a pulsed current generator. Feedback paths are provided to control constant current generators through the voltage available on both loop filter terminals. According to the present invention, pulsed current generators (I7, I8) are separated from the respective loop filter terminals (N1 , N2) by circuit breaking switching means (S1, S2), said circuit breaking switching means (S1, S2) being controlled by phase signals (UP, DOWN) outputted from the phase comparator (2).

    Abstract translation: 一种锁相环，包括相位比较器，电荷泵浦电路，环路滤波器和压控振荡器，其中环路滤波器包括与电荷泵浦电路的两个对称分支连接的两个输入端子，每个对称支路包括恒定电流发生器 和脉冲电流发生器。 提供反馈路径，通过两个环路滤波器端子上可用的电压来控制恒流发电机。 根据本发明，脉冲电流发生器（I7，I8）通过断路切换装置（S1，S2）与各个环路滤波器端子（N1，N2）分离，所述断路切换装置（S1，S2）被控制 通过从相位比较器（2）输出的相位信号（UP，DOWN）。

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