公开(公告)号：WO2005083896A1

公开(公告)日：2005-09-09

申请号：PCT/IB2005/000121

申请日：2005-01-14

Applicant: STMICROELECTRONICS S.R.L. ,  RIMI, Francesco ,  SERRATORE, Alberto ,  AVELLONE, Giuseppe ,  PAPPALARDO, Francesco ,  GALLUZZO, Agostino

Inventor： RIMI, Francesco ,  SERRATORE, Alberto ,  AVELLONE, Giuseppe ,  PAPPALARDO, Francesco ,  GALLUZZO, Agostino

IPC: H04B1/707

CPC classification number: H04B1/7083 ,  H04B1/70735 ,  H04B2201/7071

Abstract: In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (e mídamble )of said received signal (r) to an input of a correlation bank (111, 151; 203, 253; 303). There are envisaged the operations of: - sending, in a first time interval, the received signal (r) to said correlation bank (303) for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); - sending, in a second time interval, at least part (e mídamble ) of said received signal (r) to said same correlation bank (303) for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); - sending, in a second time interval, the received signal (r) to said same correlation bank (303) for executing the third operation of correlation of at least part (e midamble ) of said received signal (r) with known midamble codes (mid, MPL, MPS). Preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract translation: 为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作 代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分 所述第一，第二和第三相关操作是通过将所述接收信号（r）的至少一部分（emídamble）发送到相关库（111，...）的输入， 151; 203,253; 303）。 设想了以下操作： - 在第一时间间隔中将接收信号（r）发送到所述相关库（303），以执行所述接收信号（r）与辅同步码（SSC）的相关性的第一操作， ; - 在第二时间间隔中将所述接收信号（r）的至少一部分（emídamble）发送到所述相关相关库（303），用于执行所述接收信号（r）与已知中间码（mid）的相关性的第二操作 ，MPL，MPS）; - 接收信号（r）在第二时间间隔发送到所述相关相关库（303），用于执行所述接收信号（r）的至少部分（emidamble）与已知中间码（中间码）的中间相关的第三操作 ，MPL，MPS）。 优先应用在基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统中。

公开(公告)号：EP3270533A1

公开(公告)日：2018-01-17

申请号：EP17176174.5

申请日：2017-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe

IPC: H04L1/00

CPC classification number: H04L45/745 ,  H04L1/0053 ,  H04L1/0061 ,  H04L1/0078 ,  H04L69/22 ,  H04W52/0229 ,  Y02D70/00 ,  Y02D70/166

Abstract: A receiver circuit for extracting data (DAT) from a serial data signal (SDI) is described. The serial data signal (SDI) contains a data packet having a first or a second data packet format based on a selection signal (AS), wherein the first data packet format has a first number of bits (PRE, P1, DAT, P2, A1, P3, A2) and the second data packet format (PRE, P1, DAT, P2, A1, P3, A2, P4, A3) has a second number of bits, wherein the second data packet format comprises the bits of the first data packet format (PRE, P1, DAT, P2, A1, P3, A2) followed by one or more additional bits (P4, A3).
The receiver circuit comprises one or more shift registers (REG) having a total number of bits being equal or greater than the number of bits of the second data packet format. The receiver circuit comprises also a switching circuit (200) configured to selectively connect the serial data signal (SDI) to one of the serial inputs of the one or more shift registers (REG) as a function of the selection signal (AS). In particular, when the first data packet format has been selected and once having received the respective bits, the bits of the first data packet format are stored in given positions of the one or more shift registers (REG). The switching circuit (200) ensures moreover that, when the second data packet format has been selected and once having received the respective bits, the bits of the first data packet format included at the beginning of the second data packet format are stored in the same given positions of the one or more shift registers (REG).

Abstract translation: 描述了用于从串行数据信号（SDI）提取数据（DAT）的接收器电路。 串行数据信号（SDI）包含具有基于选择信号（AS）的第一或第二数据分组格式的数据分组，其中第一数据分组格式具有第一数量的比特（PRE，P1，DAT，P2， A1，P3，A2）和第二数据分组格式（PRE，P1，DAT，P2，A1，P3，A2，P4，A3）具有第二数量的比特，其中第二数据分组格式包括第一 数据包格式（PRE，P1，DAT，P2，A1，P3，A2），后跟一个或多个附加位（P4，A3）。 接收器电路包括一个或多个移位寄存器（RE​​G），其具有的总位数等于或大于第二数据分组格式的位数。 接收器电路还包括被配置为根据选择信号（AS）将串行数据信号（SDI）选择性地连接到一个或多个移位寄存器（RE​​G）的串行输入之一的开关电路（200）。 具体地，当第一数据分组格式已经被选择并且一旦已经接收到相应比特时，第一数据分组格式的比特被存储在一个或多个移位寄存器（RE​​G）的给定位置中。 此外，切换电路（200）确保，当已经选择了第二数据分组格式并且一旦已经接收到相应比特时，在第二数据分组格式的开始处包括的第一数据分组格式的比特被存储在相同 给定一个或多个移位寄存器（RE​​G）的位置。

公开(公告)号：EP1873627A1

公开(公告)日：2008-01-02

申请号：EP06116243.4

申请日：2006-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe ,  SALURSO, Elena ,  GUIDETTI, Elio

IPC: G06F9/38

CPC classification number: G06F9/3012 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891

Abstract: A processor architecture (10) e.g. for multimedia applications, includes a plurality of processor clusters (18a, 18b) that provide a vectorial data processing capability. The processing elements in the processor clusters (18a, 18b) are configured to process both data with a given bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) paradigm. A load unit (26) is provided for loading into the processor clusters (18a, 18b) data to be processed in the form of sets of more significant bits and less significant bits of operands to be processed according to a same instruction. An intercluster datapath (28) exchanges and/or merges data between the processor clusters (18a, 18b). The intercluster datapath (28) is scalable to activate selected ones of the processor clusters (18a, 18b), whereby the architecture (10) is adapted to operate simultaneously on SIMD, scalar and vectorial data. Preferably, the instruction subsystem (12) has instruction parallelism capability and the intercluster datapath (28) is configured for performing operations on e.g. 2*N data. Preferably, a data cache memory (34) is provided which is accessible either in a scalar mode or in a vectorial mode.

Abstract translation: 处理器架构（10） 对于多媒体应用，包括提供矢量数据处理能力的多个处理器集群（18a，18b）。 处理器集群（18a，18b）中的处理元件被配置为根据单指令多数据（SIMD）处理具有给定位长度N的数据和具有位长度N / 2，N / 4等的数据， 范例。 提供加载单元（26），用于根据相同的指令以要处理的更高有效位的集合和较低有效位的操作数的形式加载到处理器集群（18a，18b）中。 集群间数据路径（28）在处理器集群（18a，18b）之间交换和/或合并数据。 集群间数据路径（28）是可扩展的，以激活处理器集群（18a，18b）中的所选择的一个，由此架构（10）适于同时在SIMD，标量和矢量数据上操作。 优选地，指令子系统（12）具有指令并行性能，并且集群间数据通路（28）被配置为执行例如操作。 2 * N数据。 优选地，提供可以以标量模式或向量模式访问的数据高速缓存存储器（34）。

公开(公告)号：EP3331166A1

公开(公告)日：2018-06-06

申请号：EP17176189.3

申请日：2017-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe

IPC: H03K19/173

CPC classification number: H03K19/21 ,  G08C2201/91 ,  H03K19/1733 ,  H03K19/1737 ,  H03K2217/94021 ,  H04L61/2038 ,  H04L61/6072

Abstract: The disclosure relates to a system comprising a processing circuit and a circuit (230a) configured to provide at output a given number N A2 of bits of configuration information (A_CFG) to be used by said processing circuit. The circuit (230a) comprises a non-volatile programmable memory (2300) providing at output a first group (A_CFG1) of N A2 bits.
The circuit (230a) may comprise also N A2 terminals for receiving a second group (A_CFG2) of N 42 bits and N A2 logic gates (2304). In this case, a first input terminal of each logic gate (2304) may be connected to a respective bit of the output of the non-volatile programmable memory (2300) providing at output the first group (A_CFG1) of N A2 bits, and a second input terminal of each logic gate (2304) may be connected to a respective terminal of the N A2 terminals for receiving the second group of N A2 bits.
In addition, or alternatively, the circuit (230a) may comprises a further memory (2306) providing at output a third group (A_CFG3) of N A2 bits and N A2 logic gates (2308). In this case, a first input terminal of each logic gate (2308) may be connected to a respective bit of the output of the non-volatile programmable memory (2300) providing at output the first group (A_CFG1) of N A2 bits, and a second input terminal of each logic gate (2308) may be connected to a respective bit of the output of the further memory (2306) providing at output the third group (A_CFG3) of N A2 bits.

公开(公告)号：EP1873648A1

公开(公告)日：2008-01-02

申请号：EP06116248.3

申请日：2006-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe ,  SALURSO, Elena ,  GUIDETTI, Elio

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0886 ,  Y02D10/13

Abstract: A data cache memory coupled to a processor architecture including a plurality of processor clusters (Cluster0,..., Cluster3) is adapted to operate simultaneously on scalar and vectorial data by providing in the data cache memory data locations for storing therein data for processing by the architecture, and accessing the data locations in the data cache memory either in a scalar mode or in a vectorial mode. This is done preferably by explicitly mapping those locations of the cache memory considered as scalar and those locations of the cache memory considered as vectorial.

Abstract translation: 耦合到包括多个处理器集群（Cluster0，...，Cluster3）的处理器架构的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供数据位置来同时处理标量和矢量数据，用于存储其中的数据以供处理 并且以标量模式或向量模式访问数据高速缓冲存储器中的数据位置。 这优选地通过明确地映射被认为是标量的高速缓冲存储器的那些位置，以及被认为是矢量的高速缓冲存储器的那些位置。

公开(公告)号：EP3331166B1

公开(公告)日：2020-12-02

申请号：EP17176189.3

申请日：2017-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe

IPC: H03K19/173

公开(公告)号：EP3270533B1

公开(公告)日：2019-02-20

申请号：EP17176174.5

申请日：2017-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe

IPC: H04L1/00

公开(公告)号：EP3425360A1

公开(公告)日：2019-01-09

申请号：EP18181888.1

申请日：2018-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： PAPPALARDO, Francesco ,  PENNISI, Agatino ,  GUIDETTI, Elio ,  DORIANI, Angelo

IPC: G01L1/14 ,  G01M5/00

Abstract: A capacitive sensor (1), for monitoring stresses acting in a construction structure when introduced into the construction structure, has a multi-layer structure provided with an upper conductive layer (2a), defining an upper outer surface of the sensor; a lower conductive layer (2b), defining a lower outer surface of the sensor; at least a first layer (5a) of insulating material, in contact with the upper conductive layer; at least a second layer (5b) of insulating material, in contact with the lower conductive layer; at least a first plate layer (4a), of conductive material; at least a second plate layer (4b), of conductive material; at least one dielectric layer (6), interposed between the first plate layer and the second plate layer to define at least one detection capacitor (C) inside the multi-layer structure of the sensor; wherein the upper and lower conductive layers are designed to jointly define an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.