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    CAPACITIVE PRESSURE SENSOR FOR MONITORING CONSTRUCTION STRUCTURES, PARTICULARLY MADE OF CONCRETE
    1.
    发明公开
    CAPACITIVE PRESSURE SENSOR FOR MONITORING CONSTRUCTION STRUCTURES, PARTICULARLY MADE OF CONCRETE 审中-公开

    公开(公告)号：EP3425360A1

    公开(公告)日：2019-01-09

    申请号：EP18181888.1

    申请日：2018-07-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： PAPPALARDO, Francesco ,  PENNISI, Agatino ,  GUIDETTI, Elio ,  DORIANI, Angelo

    IPC: G01L1/14 ,  G01M5/00

    Abstract: A capacitive sensor (1), for monitoring stresses acting in a construction structure when introduced into the construction structure, has a multi-layer structure provided with an upper conductive layer (2a), defining an upper outer surface of the sensor; a lower conductive layer (2b), defining a lower outer surface of the sensor; at least a first layer (5a) of insulating material, in contact with the upper conductive layer; at least a second layer (5b) of insulating material, in contact with the lower conductive layer; at least a first plate layer (4a), of conductive material; at least a second plate layer (4b), of conductive material; at least one dielectric layer (6), interposed between the first plate layer and the second plate layer to define at least one detection capacitor (C) inside the multi-layer structure of the sensor; wherein the upper and lower conductive layers are designed to jointly define an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.

    A clustered SIMD processor architecture
    2.
    发明公开
    A clustered SIMD processor architecture 有权
    SIMD-Prozessorarchitektur mit gruppierten Verarbeitungseinheiten

    公开(公告)号：EP1873627A1

    公开(公告)日：2008-01-02

    申请号：EP06116243.4

    申请日：2006-06-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe ,  SALURSO, Elena ,  GUIDETTI, Elio

    IPC: G06F9/38

    CPC classification number: G06F9/3012 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891

    Abstract: A processor architecture (10) e.g. for multimedia applications, includes a plurality of processor clusters (18a, 18b) that provide a vectorial data processing capability. The processing elements in the processor clusters (18a, 18b) are configured to process both data with a given bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) paradigm. A load unit (26) is provided for loading into the processor clusters (18a, 18b) data to be processed in the form of sets of more significant bits and less significant bits of operands to be processed according to a same instruction. An intercluster datapath (28) exchanges and/or merges data between the processor clusters (18a, 18b). The intercluster datapath (28) is scalable to activate selected ones of the processor clusters (18a, 18b), whereby the architecture (10) is adapted to operate simultaneously on SIMD, scalar and vectorial data. Preferably, the instruction subsystem (12) has instruction parallelism capability and the intercluster datapath (28) is configured for performing operations on e.g. 2*N data. Preferably, a data cache memory (34) is provided which is accessible either in a scalar mode or in a vectorial mode.

    Abstract translation: 处理器架构（10） 对于多媒体应用，包括提供矢量数据处理能力的多个处理器集群（18a，18b）。 处理器集群（18a，18b）中的处理元件被配置为根据单指令多数据（SIMD）处理具有给定位长度N的数据和具有位长度N / 2，N / 4等的数据， 范例。 提供加载单元（26），用于根据相同的指令以要处理的更高有效位的集合和较低有效位的操作数的形式加载到处理器集群（18a，18b）中。 集群间数据路径（28）在处理器集群（18a，18b）之间交换和/或合并数据。 集群间数据路径（28）是可扩展的，以激活处理器集群（18a，18b）中的所选择的一个，由此架构（10）适于同时在SIMD，标量和矢量数据上操作。 优选地，指令子系统（12）具有指令并行性能，并且集群间数据通路（28）被配置为执行例如操作。 2 * N数据。 优选地，提供可以以标量模式或向量模式访问的数据高速缓存存储器（34）。

    A method and arrangement for cache memory management, related processor architecture
    5.
    发明公开
    A method and arrangement for cache memory management, related processor architecture 有权
    Verfahren und AnordnungfürCachespeicherverwaltung und entsprechende Prozessorarchitektur

    公开(公告)号：EP1873648A1

    公开(公告)日：2008-01-02

    申请号：EP06116248.3

    申请日：2006-06-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： PAPPALARDO, Francesco ,  NOTARANGELO, Giuseppe ,  SALURSO, Elena ,  GUIDETTI, Elio

    IPC: G06F12/08

    CPC classification number: G06F12/084 ,  G06F12/0886 ,  Y02D10/13

    Abstract: A data cache memory coupled to a processor architecture including a plurality of processor clusters (Cluster0,..., Cluster3) is adapted to operate simultaneously on scalar and vectorial data by providing in the data cache memory data locations for storing therein data for processing by the architecture, and accessing the data locations in the data cache memory either in a scalar mode or in a vectorial mode. This is done preferably by explicitly mapping those locations of the cache memory considered as scalar and those locations of the cache memory considered as vectorial.

    Abstract translation: 耦合到包括多个处理器集群（Cluster0，...，Cluster3）的处理器架构的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供数据位置来同时处理标量和矢量数据，用于存储其中的数据以供处理 并且以标量模式或向量模式访问数据高速缓冲存储器中的数据位置。 这优选地通过明确地映射被认为是标量的高速缓冲存储器的那些位置，以及被认为是矢量的高速缓冲存储器的那些位置。

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