公开(公告)号：EP1363330A2

公开(公告)日：2003-11-19

申请号：EP03425299.9

申请日：2003-05-12

Applicant: STMicroelectronics S.r.l.

Inventor： Aiello, Natale ,  Patti, Davide

IPC: H01L27/02 ,  H01L29/94

CPC classification number: H01L27/0676 ,  H01L29/94

Abstract: A capacitor for sensing the substrate voltage is efficiently and economically realized simply by isolating a portion or segment of the metal layer that normally covers the heavily doped perimetral region of electric field equalization and, in correspondence of such a metal segment isolated by the remaining portion, by not removing preventively the isolation dielectric layer of silicon oxide from the surface of the semiconductor substrate, as it is normally done on the remaining portion of the perimetral edge region before depositing the metal. The unremoved layer of isolated silicon oxide becomes the dielectric layer of the so constituted capacitor, a plate of which is the heavily doped perimetral region that is electrically connected to the substrate (drain or collector region) while the other plate is constituted by the segment of metal, isolated from the remaining metal layer defined directly over the heavily doped perimetral region.

Abstract translation: 用于感测基板电压的电容器简单地通过隔离通常覆盖重掺杂的电场均衡的周边区域的金属层的部分或段来有效且经济地实现，并且对应于由剩余部分隔离的这种金属段， 通过不从半导体衬底的表面预防性除去氧化硅的隔离电介质层，因为通常在沉积金属之前在周边边缘区域的剩余部分上进行。 孤立的氧化硅（12）的未被移除的层变成所构成的电容器的电介质层，其电极是与衬底（漏极或集电极区域）电连接的重掺杂的周边区域（4），而另一个板 由金属（4'）的部分构成，与直接在重掺杂的周边区域（4）上限定的剩余金属层分离。

公开(公告)号：EP1061587A1

公开(公告)日：2000-12-20

申请号：EP99830367.1

申请日：1999-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide ,  Valvo, Giuseppina

IPC: H01L31/118 ,  H01L25/04

CPC classification number: H01L31/115

Abstract: A particle detector formed in a chip of semiconductor material comprises:

a first layer (42) with a first type of conductivity (n) having a surface on the first major surface of the chip,
a second layer (40) with the first type of conductivity (n) having a surface on the second major surface of the chip,
a third layer (41) with the first type of conductivity (n) having a resistivity lower than those of the first and second layers and disposed between the first layer (42) and the second layer (40),
a first region (46) with a second type of conductivity (p), extending from the first surface into the first layer (42),
a second region (45) with the second type of conductivity (p), extending from the second major surface into the second layer (40), and
first (48), second (50,51) and third (43,47) electrical connection means for connection with the first region (46) with the second region (45), and with the third layer (41), respectively.

To produce a position detector which does not require a large number of connections, the second electrical connection means comprise two electrodes (50,51) arranged a predetermined distance apart on the surface of the second region (45).

Abstract translation: 形成在半导体材料芯片中的粒子检测器包括：具有在芯片的第一主表面上的表面的第一导电类型的第一层（42），具有第一类型的第二层（40） 具有在芯片的第二主表面上的表面的导电性（n），具有比第一和第二层的电阻率低的第一类型导电性（n）的第三层（41），并且设置在第一层 42）和第二层（40），具有从第一表面延伸到第一层（42）的具有第二类型导电性（p）的第一区域（46），具有第二类型 从第二主表面延伸到第二层（40）的电导率（p）和用于与第一区域（46）连接的第一（48），第二（50,51）和第三（43,47）电连接装置， 与第二区域（45）以及第三层（41）分别连接。 为了产生不需要大量连接的位置检测器，第二电连接装置包括在第二区域（45）的表面上隔开预定距离布置的两个电极（50,51）。

公开(公告)号：EP0837507B1

公开(公告)日：2004-08-18

申请号：EP96830536.7

申请日：1996-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide

IPC: H01L29/73 ,  H01L21/331

CPC classification number: H01L29/66303 ,  H01L29/7304

公开(公告)号：EP1198010A1

公开(公告)日：2002-04-17

申请号：EP00830661.5

申请日：2000-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0852 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7816 ,  H01L29/7824

Abstract: A semiconductor power device (3) comprising a P-type substrate (4) and an N-type epitaxial layer (5) comprises a lateral DMOS transistor (1,2) having a source region (10,11) and a drain region (12) formed in the epitaxial layer (5) and a body region (8,9) housing the source region (10,11). Between the source region (10,11) and the drain region (12) is present an insulating region (13,14) extending from a top surface (15) of the epitaxial layer (5) to the substrate (4). The insulating region (13,14) has an opening in a longitudinal direction (Y) defining a channelling region for a current I D flowing between the source region (10,11) and the drain region (12) of the lateral DMOS transistor (1,2).

Abstract translation: 包括P型衬底（4）和N型外延层（5）的半导体功率器件（3）包括具有源极区（10,11）和漏极区（10,11）的横向DMOS晶体管（1,2） 形成在外延层（5）中的体区域（8,9）和容纳源区域（10,11）的体区域（8,9）。 在源区（10,11）和漏区（12）之间存在从外延层（5）的顶表面（15）延伸到衬底（4）的绝缘区域（13,14）。 绝缘区域（13,14）在长度方向（Y）上具有开口，该开口限定用于在横向DMOS晶体管（1）的源极区域（10,11）和漏极区域（12）之间流动的电流ID的沟道区域 ，2）。

公开(公告)号：EP1134799A1

公开(公告)日：2001-09-19

申请号：EP00830197.0

申请日：2000-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Coffa, Salvatore ,  Patti, Davide

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  Y10S438/962

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process comprises, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between .1 keV and 7keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract translation: 一种用于形成硅的薄层过程在氧化物层纳米晶体中游离缺失盘。 该方法包括，在半导电衬底，热氧化衬底的第一部分成氧化物层，氧化物层中形成硅离子，以及热处理所述硅离子，成为硅纳米晶体的薄层。 在本发明方法的硅离子的形成是通过将硅离子注入到氧化的离子注入处的0.1千电子伏和7keV之间，并且优选1至5千电子伏电离能。 这使得硅原子结合成一个较低的温度比其他可能的。 此外，纳米晶体的一个以上的层可以通过在多于一个能级执行多于一个的注入来形成。 本发明的实施例可以被用于形成具有非常小的尺寸非常高质量的非易失性存储器装置。

公开(公告)号：EP1557560A1

公开(公告)日：2005-07-27

申请号：EP04425035.5

申请日：2004-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： Torres, Antonino ,  Patti, Davide

IPC: F02P3/055 ,  H03K17/567

CPC classification number: H03K17/0828 ,  F02D2041/2075 ,  F02P3/0435

Abstract: The present invention relates to a circuit (20) for dynamic control of a power transistor in applications for high voltage and of the type wherein a power transistor (TR1) has a conduction terminal (C) connected to a load and a control terminal (G1) receiving a driving signal from a driver block (4) activated by a trigger signal (Vin) received on a circuit input terminal (IN1). Advantageously, the circuit (20) comprises a JFET component (TR2) inserted between the conduction (C) and control (G1) terminal of the power transistor (TR1) and equal to a resistance with non-linear feature.
Moreover, the JFET component (TR2) is monolithically integrated in the structure of said power transistor (TR1).

Abstract translation: 本发明涉及一种用于在高电压应用中动态控制功率晶体管的电路（20），其中功率晶体管（TR1）具有连接到负载的导通端（C）和控制端（G1 接收由在电路输入端子（IN1）上接收的触发信号（Vin）激活的驱动器块（4）的驱动信号。 有利地，电路（20）包括插入在功率晶体管（TR1）的导通（C）和控制（G1）端子之间并等于具有非线性特征的电阻的JFET部件（TR2）。 此外，JFET部件（TR2）被单片集成在所述功率晶体管（TR1）的结构中。

公开(公告)号：EP1005091A1

公开(公告)日：2000-05-31

申请号：EP98830690.8

申请日：1998-11-17

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide ,  Pinto, Angelo

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66666 ,  H01L21/76221 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/7827

Abstract: The following steps are performed on a wafer of semiconductor material having a layer (1) with n conductivity: a) implanting n impurity ions and p impurity ions in an area of the layer and subjecting the wafer to a high-temperature treatment; the impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first, p region (49) and a second, n region (50) which forms a pn junction with the first region (49); b) hollowing out a trench (43) which intersects the first region (49) and the second region (50), c) forming a dielectric coating (44) on the lateral surface of the trench (43), d) depositing electrically-conductive material (51) in the trench (43) in contact with the dielectric (44), and e) forming elements (60, 61, 62) for electrical contact with the layer (1), with the second region (50), and with the electrically-conductive material (51) inside the trench (43), in order to produce drain (D), source (S) and gate (G) electrodes of the MOSFET, respectively. A submicrometric vertical-channel MOSFET of optimal quality and reproducibility is thus produced by a method compatible with DPSA technology.

Abstract translation: 在具有n导电性的层（1）的半导体材料的晶片上进行以下步骤：a）在层的区域中注入n个杂质离子和p杂质离子，并对晶片进行高温处理; 杂质，注入剂量和能量，以及高温处理时间和温度，以形成与第一区域形成pn结的第一p区（49）和第二n区（50） 49）; b）挖空与第一区域（49）和第二区域（50）相交的沟槽（43），c）在沟槽（43）的侧表面上形成电介质涂层（44），d） 与所述电介质（44）接触的所述沟槽（43）中的导电材料（51），以及e）与所述第二区域（50）形成用于与所述层（1）电接触的元件（60,61,62） 并且沟槽（43）内部的导电材料（51）分别产生MOSFET的漏极（D），源极（S）和栅极（G）电极。 因此，通过与DPSA技术兼容的方法产生了具有最佳质量和重现性的亚微米级垂直沟道MOSFET。

公开(公告)号：EP1557560B1

公开(公告)日：2007-10-17

申请号：EP04425035.5

申请日：2004-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： Torres, Antonino ,  Patti, Davide

IPC: F02P3/055 ,  H03K17/567

CPC classification number: H03K17/0828 ,  F02D2041/2075 ,  F02P3/0435

公开(公告)号：EP1061587B1

公开(公告)日：2007-03-28

申请号：EP99830367.1

申请日：1999-06-15

Applicant: STMicroelectronics S.r.l.

Inventor： Patti, Davide ,  Valvo, Giuseppina

IPC: H01L31/118 ,  H01L25/04

CPC classification number: H01L31/115

公开(公告)号：EP1727203A1

公开(公告)日：2006-11-29

申请号：EP05425365.3

申请日：2005-05-24

Applicant: STMicroelectronics S.r.l.

Inventor： Torres, Antonino ,  Sueri, Stefano ,  Patti, Davide

IPC: H01L27/02 ,  H03K17/0814 ,  F02P3/04

CPC classification number: F02P3/0435 ,  F02D2041/2058 ,  F02D2041/2075 ,  F02P3/02 ,  H03K17/08128

Abstract: A power IGBT device is described being monolithically integrated and comprising an input terminal (I10) suitable to receive an input voltage (Vin) and an output terminal (O10) suitable to supply a current (Iout) with limited and predetermined highest value. Such IGBT device comprising an IGBT power element (2) inserted between said output terminal (O10) and a supply reference (GND) and having a control terminal (15) connected to the input terminal (110) by means of a control circuit (12) comprising at least a transistor (18) inserted between the control terminal (15) and the supply reference (GND) and a resistive element (Rc) inserted between the input terminal (I10) and the control terminal (15).

Abstract translation: 电力IGBT器件被描述为单片集成的，并且包括适于接收输入电压（Vin）的输入端（I10）和适于提供具有有限和预定最高值的电流（Iout）的输出端（O10）。 这种IGBT器件包括插入在所述输出端子（O10）和电源基准（GND）之间并且具有通过控制电路（12）连接到输入端子（110）的控制端子（15）的IGBT功率元件（2） ）包括插入在控制端子（15）和供电基准（GND）之间的至少一个晶体管（18）和插入在输入端子（I10）和控制端子（15）之间的电阻元件（Rc）。