Abstract:
A voltage shifter (20) has a supply line receiving a supply voltage (VH) that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage (2) is connected to an output branch (6) and to a selection circuit (5), which receives a selection signal (SEL) that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line (34), which receives a reference voltage (WB) that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. A uncoupling stage (23) is arranged between the latch stage (2) and the selection circuit (5) and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value.
Abstract:
A voltage regulator (40; 50) for a regulated voltage generator (2) configured for generating an operating voltage (V OUT ), the voltage regulator comprising: a variable comparison voltage generator (42), configured for generating on an output (48c) of its own a comparison voltage (V C ); a partition branch (44; 52) including a plurality of active devices (T 1 , ..., T M-1 , T M ) of a resistive type, configured for receiving at input the operating voltage (V OUT ) and supplying at output an intermediate voltage (V R ) correlated to the operating voltage; and a comparator (46), configured for receiving at input the comparison voltage (V C ) and the intermediate voltage (V R ) and supplying at output a regulation signal (V ON/OFF ) for the regulated-voltage generator (2).
Abstract:
Described herein is a method for biasing an EEPROM array (10) formed by memory cells (2) arranged in rows and columns, each operatively coupled to a first switch (3) and to a second switch (4) and having a first current-conduction terminal selectively connectable to a bitline (BL) through the first switch (3) and a control terminal selectively connectable to a gate-control line (Cgt) through the second switch (4), wherein associated to each row are a first wordline (WL seltr) and a second wordline (WL bsw), connected to the control terminals of the first switches (3) and, respectively, of the second switches (4) operatively coupled to the memory cells (2) of the same row. The method envisages selecting at least one memory cell (2) for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage (V DD ) and are a function of the given memory operation.