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1.Method for biasing an EEPROM non-volatile memory array and corresponding EEPROM non-volatile memory device 有权
Title translation: 偏置非易失性EEPROM存储器阵列和对应的非易失性EEPROM存储器阵列的方法公开(公告)号:EP2302635B1
公开(公告)日:2016-01-13
申请号:EP09425359.8
申请日:2009-09-18
Applicant: STMicroelectronics Srl
Inventor: Lo Giudice, Gianbattista , Castaldo, Enrico , Conte, Antonino
CPC classification number: G11C16/0433 , G11C16/10 , G11C16/16
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2.Low consumption voltage regulator for a high voltage charge pump, voltage regulation method, and memory device provided with said voltage regulator 有权
Title translation: 电压调节器具有低功耗高压电荷泵电压控制方法和存储设备具有这样的电压调节器公开(公告)号:EP2299576B1
公开(公告)日:2014-06-18
申请号:EP09425361.4
申请日:2009-09-18
Applicant: STMicroelectronics Srl
Inventor: Conte, Antonino , Di Martino, Alberto José , Castaldo, Enrico
IPC: H02M3/07
CPC classification number: H02M3/07 , G11C5/145 , H02M2001/0025
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公开(公告)号:EP1988548B1
公开(公告)日:2010-08-25
申请号:EP08007685.4
申请日:2008-04-21
Applicant: STMICROELECTRONICS SA , STMicroelectronics Srl
Inventor: La Rosa, Francesco , Conte, Antonino
IPC: G11C16/22
CPC classification number: G11C16/225 , G11C16/102
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4.Electric circuit for generating low voltage and high frequency phases in a charge pump, in particular for supplies lower than 1V 有权
Title translation: 对于低于1 V在电荷泵产生低电压和高频级,特别是用于电源电压的电路公开(公告)号:EP2166656B1
公开(公告)日:2013-04-10
申请号:EP08425608.0
申请日:2008-09-18
Applicant: STMicroelectronics Srl
Inventor: Conte, Antonino , Ucciardello, Carmelo , Matranga, Giovanni
IPC: H02M3/07
CPC classification number: H02M3/073 , H02M2003/077
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公开(公告)号:EP1988549B1
公开(公告)日:2010-10-27
申请号:EP08007686.2
申请日:2008-04-21
Applicant: STMICROELECTRONICS SA , STMicroelectronics Srl
Inventor: La Rosa, Francesco , Conte, Antonino
IPC: G11C16/22
CPC classification number: G11C16/225 , G11C16/102
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公开(公告)号:EP1988550B1
公开(公告)日:2010-08-25
申请号:EP08007687.0
申请日:2008-04-21
Applicant: STMICROELECTRONICS SA , STMicroelectronics Srl
Inventor: La Rosa, Francesco , Conte, Antonino
IPC: G11C16/22
CPC classification number: G11C16/225 , G11C16/102
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7.Circuit for generating a temperature-compensated voltage reference, in particular for applications with supply voltages lower than 1V 有权
Title translation: 电路,用于产生温度补偿的电压基准,特别是用于与低于1V的电源电压应用公开(公告)号:EP2120124B1
公开(公告)日:2014-07-09
申请号:EP08425331.9
申请日:2008-05-13
Applicant: STMicroelectronics Srl
Inventor: Conte, Antonino , Miccichè, Mario , Grasso, Rosario Roberto
IPC: G05F3/30
CPC classification number: G05F3/30
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8.Sense-amplifier circuit for non-volatile memories that operates at low supply voltages 有权
Title translation: 用于非易失性存储器,其在低电源电压下工作的读出放大器电路公开(公告)号:EP2299450B1
公开(公告)日:2013-03-27
申请号:EP09425360.6
申请日:2009-09-18
Applicant: STMicroelectronics Srl
Inventor: Lo Giudice, Gianbattista , Conte, Antonino , Micciche', Mario , Rinaldi, Stefania
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公开(公告)号:EP2383747B1
公开(公告)日:2012-12-19
申请号:EP11164292.2
申请日:2011-04-29
Applicant: STMicroelectronics Srl
Inventor: Castaldo, Enrico , Conte, Antonino , Lo Giudice, Gianbattista , Rinaldi, Stefania
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10.Sense-amplifier circuit for non-volatile memories that operates at low supply voltages 有权
Title translation: 用于非易失性存储器,其在低电源电压下工作的读出放大器电路公开(公告)号:EP2299450A8
公开(公告)日:2011-05-11
申请号:EP09425360.6
申请日:2009-09-18
Applicant: STMicroelectronics Srl
Inventor: Lo Giudice, Gianbattista , Conte, Antonino , Micciche', Mario , Rinaldi, Stefania
Abstract: A sense-amplifier circuit (1) for a non-volatile memory is provided with: a comparison stage (15, 16a-16b) that executes, during a comparison step, a comparison between a cell current (I cell ) that flows in a memory cell (2) and through an associated bitline (BL), and a reference current (I ref ), for supplying an output signal (Out sense) indicating the state of the memory cell (2); and a precharging stage (18a-18b, 22a-22b), which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline (BL) so as to charge a capacitance thereof; the comparison stage is formed by a first comparison transistor (16a) and by a second comparison transistor (16b), which are coupled in current-mirror configuration respectively to a first differential output (Out1) and to a second differential output (Out2), through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline (BL) as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror.
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