公开(公告)号：KR1020050058867A

公开(公告)日：2005-06-17

申请号：KR1020030090854

申请日：2003-12-12

Applicant: 삼성전자주식회사

Inventor： 황홍기

IPC: H03M1/12

CPC classification number: H03M1/1225 ,  H03M2201/173

Abstract: 본 발명은 아날로그-디지털 변환에 관한 것으로, 더욱 상세히는 다채널 아날로그-디지털 변환장치에 수신되는 입력 신호의 디지털신호로의 변환을 각 채널별로 우선순위를 두어서 수행하다가 필요한 경우에 우선순위를 바꾸어서 아날로그-디지털변환과정을 수행하는 아날로그-디지털 변환 제어에 관한 것이다.

公开(公告)号：KR1020090042763A

公开(公告)日：2009-04-30

申请号：KR1020090002405

申请日：2009-01-12

Applicant: 한국전자통신연구원

Inventor： 서재현 ,  임형수 ,  김흥묵 ,  이용태 ,  박성익 ,  임종수 ,  이수인

IPC: H04N21/43 ,  H04N7/015

CPC classification number: H03M1/662 ,  H03M2201/173 ,  H03M2201/30 ,  H04H20/65 ,  H04N21/435

Abstract: A transmission method and a device, and a recording medium and a receiving device of digital broadcasting signal are provided to offer different transmission modes for frequency domain and time domain respectively. An allocation unit assigns more than one sub-band and more than one symbol to a modulated service data which is outputted from M digital modulator(S430). An IFFT(Inverse Fast Fourier Transform) converts a signal of a frequency domain to a signal of the time domain about the M service data outputted from the sub-band allocation unit(S440). A frame generator generates a plurality of symbol durations into a frame body of one transfer frame(S450). The frame generator generates a frame header which includes the information about each of M services(S460). A D/A converter converts a transfer frame of a digital signal outputted from the frame generator into an analog signal(S470). The D/A converter transmits the transfer frame converted into an analog signal to a receiving device.

Abstract translation: 提供传输方法和装置，以及数字广播信号的记录介质和接收装置，以分别为频域和时域提供不同的传输模式。 分配单元向从M数字调制器输出的调制业务数据分配多于一个子带和多于一个符号（S430）。 IFFT（逆快速傅里叶变换）将频域的信号转换为关于从子带分配单元输出的M服务数据的时域的信号（S440）。 帧生成器将多个符号持续时间生成到一个传送帧的帧体中（S450）。 帧生成器生成包括关于每个M服务的信息的帧头（S460）。 D / A转换器将从帧发生器输出的数字信号的传送帧转换为模拟信号（S470）。 D / A转换器将转换成模拟信号的传送帧发送到接收设备。

公开(公告)号：KR1020020065063A

公开(公告)日：2002-08-13

申请号：KR1020010005408

申请日：2001-02-05

Applicant: 엘지이노텍 주식회사

Inventor： 정영삼

IPC: H03M1/12

CPC classification number: H03M1/1215 ,  H03M2201/173 ,  H03M2201/932

Abstract: PURPOSE: An interface device for multi channel data processing is provided, which enables a DSP(Digital Signal Processor) to read ADC(Analog Digital Converter) data in a high speed. CONSTITUTION: A timing generator(7) generates an ADC clock(ADC_CLKIN) and an ADC synchronous signal(ADC_FSI) and an interrupt signal(IIOF_) by receiving a main clock(MAIN_CLK) and a start signal(START) and a reply signal(CLK_BACK) and an ADC inform signal(ADC_FSO), and performs a data latch enable control. A serial/parallel data converter(8) latches digital serial data(SD00-SD09) of the analog digital converter according to the latch enable control, and converts the latched serial data into parallel data(D0-D15) according to output enable signals(OEN0-OEN9) inputted from the digital signal processor through a decoder. AND gate circuits(9,10) generate a test signal(/OE_TEST) by decoding the output enable signal.

Abstract translation: 目的：提供用于多通道数据处理的接口设备，使DSP（数字信号处理器）能够高速读取ADC（模数转换器）数据。 构成：定时发生器（7）通过接收主时钟（MAIN_CLK）和起始信号（START）和应答信号（START）和时钟发生器（7）产生ADC时钟（ADC_CLKIN）和ADC同步信号（ADC_FSI）和中断信号（IIOF_） CLK_BACK）和ADC通知信号（ADC_FSO），并执行数据锁存使能控制。 串行/并行数据转换器（8）根据锁存使能控制锁存模拟数字转换器的数字串行数据（SD00-SD09），根据输出使能信号将锁存的串行数据转换为并行数据（D0-D15） OEN0-OEN9）通过解码器从数字信号处理器输入。 与门电路（9,10）通过解码输出使能信号来产生测试信号（/ OE_TEST）。