公开(公告)号：US20130248887A1

公开(公告)日：2013-09-26

申请号：US13845445

申请日：2013-03-18

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS PTE LTD

Inventor： Romain Coffy ,  Eric Saugier ,  Hk Looi ,  Norbert Chevrier

IPC: H01L31/0203 ,  H01L31/18

CPC classification number: H01L31/0203 ,  G01S7/481 ,  G01S17/026 ,  H01L25/167 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/181 ,  H03K17/941 ,  H03K2017/9455 ,  H03K2217/94026 ,  H03K2217/94112 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.

Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。

公开(公告)号：US08535980B2

公开(公告)日：2013-09-17

申请号：US12977697

申请日：2010-12-23

Applicant: Puay Gek Chua ,  Yonggang Jin

Inventor： Puay Gek Chua ,  Yonggang Jin

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T408/566 ,  H01L2924/014 ,  H01L2924/00

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract translation: 提供了一种用于制造半导体封装的工艺，其包括在重构的晶片中钻孔盲孔，将覆盖在晶片上的干膜抗蚀剂粘附在孔上，以及图案化膜以暴露每个孔周围的空间。 然后通过在胶片的表面上擦拭一定量的糊料，将导电浆料填充到孔和空间中，使得糊料被迫进入空间和孔。 孔周围的空间限定了其厚度受薄膜厚度限制的接触垫，优选为约10μm或更小。 为了防止糊料在孔中捕获气穴，擦拭过程可以在空气中进行大量或全部空气的​​室中进行。 在固化糊料之后，晶片从后面变薄以露出孔中的固化糊料。

公开(公告)号：US08502394B2

公开(公告)日：2013-08-06

申请号：US12651080

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die.

Abstract translation: 多堆叠半导体晶片组件在普通封装脚印上增强了板级可靠性和集成电气功能。 多层半导体晶片组件包括具有阶梯状上表面的底模。 台阶状上表面包括基部区域和相对于基底区域升高的阶梯状区域。 基部区域包括多个附接结构，其尺寸和形状被容纳以接纳导电球。 上模具堆叠在底模上方。 上模具包括多个附接结构，其尺寸和形状适于容纳导电球，并且被布置成与底模的附接结构对准。 导电球连接到底模的附接结构和上模的附接结构。

公开(公告)号：US08492181B2

公开(公告)日：2013-07-23

申请号：US13335548

申请日：2011-12-22

Applicant: Anandan Ramasamy ,  KahWee Gan ,  Hk Looi ,  David Gani

Inventor： Anandan Ramasamy ,  KahWee Gan ,  Hk Looi ,  David Gani

IPC: H01L21/00

CPC classification number: H01L25/167 ,  H01L23/5389 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14683 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.

Abstract translation: 一种形成嵌入式晶片级光学封装的方法包括将传感器芯片，PCB条和LED粘贴在层压在载体上的粘合带上，将传感器管芯的两个感光传感器之间的坝连接，封装传感器管芯，PCB条 ，LED和封装层中的坝，使载体脱粘，研磨封装层的顶表面，通过封装层形成通孔到传感器裸片和LED，用导电材料填充通孔，使顶表面金属化 封装层的顶表面的电介质涂层，封装层的底表面的电介质涂层，图案化封装层底表面的电介质涂层，以及镀覆底表面的图案化电介质涂层 的封装层。

公开(公告)号：US20130169312A1

公开(公告)日：2013-07-04

申请号：US13341317

申请日：2011-12-30

Applicant: Yann Desprez-Le-Goarant ,  Jingfeng Gong

Inventor： Yann Desprez-Le-Goarant ,  Jingfeng Gong

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/00361 ,  G06F3/0416 ,  H03K19/00392

Abstract: A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.

Abstract translation: 电路包括多个逻辑门和驱动电路。 多个逻辑门耦合在第一供应节点和第二供应节点之间。 每个逻辑门具有至少一个输入，并在逻辑状态转换期间消耗短路电流。 驱动电路耦合到多个逻辑门的输入，以将输入信号的副本传送到每个逻辑门，其中输入信号复制在基本上不同的时间到达逻辑门的输入端。 电路可以结合在触摸屏面板和显示器中。

公开(公告)号：US20130168899A1

公开(公告)日：2013-07-04

申请号：US13340319

申请日：2011-12-29

Applicant: Jerome Teysseyre ,  Glenn de los Reyes

Inventor： Jerome Teysseyre ,  Glenn de los Reyes

IPC: B29C45/24 ,  B29C45/26

CPC classification number: B29C45/17 ,  B29C45/1753 ,  B29C45/2701

Abstract: A top-gate molding system for encapsulating semiconductor devices includes a plurality of mold cavities formed between a middle plate and a bottom plate, and a runner system formed between an upper plate and the middle plate. The runner system includes a runner with a plurality of reservoirs along its length, with a gate extending from each of the reservoirs to one of the cavities. A particle trap is positioned on the bottom of the runner between a sprue and a first one of the reservoirs, to capture contaminating particles in a flow of molding compound before the particles enter any of the reservoirs. The particle trap can be, for example, a notch or a channel extending transversely across the bottom of the runner, or a dummy reservoir upstream of the first of the plurality of reservoirs.

Abstract translation: 用于封装半导体器件的顶栅模制系统包括形成在中间板和底板之间的多个模腔，以及形成在上板和中板之间的浇道系统。 流道系统包括沿着其长度具有多个储存器的流道，门从每个储存器延伸到其中一个空腔。 颗粒捕集器位于浇道和第一储存器之间的流道底部，以在颗粒进入任何储存器之前捕获模制化合物流中的污染颗粒。 颗粒捕获器可以是例如横向延伸穿过流道的底部的凹口或通道，或者在多个储存器中的第一个的上游的虚拟储存器。

公开(公告)号：US20130168355A1

公开(公告)日：2013-07-04

申请号：US13339797

申请日：2011-12-29

Applicant: Ying Yu ,  Tien Choy Loh ,  Shian Yeu Kam

Inventor： Ying Yu ,  Tien Choy Loh ,  Shian Yeu Kam

IPC: B44C1/22

CPC classification number: C09K13/00 ,  H01L21/30608

Abstract: Methods and apparatus for etching materials using tetramethylammonium hydroxide (TMAH) are described. The methods may involve including an additive when applying the TMAH to the material to be etched. The additive may be a gas, and in in some situations may be clean dry air. The clean dry air may be provided with the TMAH to minimize or prevent the formation of hillocks in the etched structure. Apparatus for performing the methods are also described.

Abstract translation: 描述了使用四甲基氢氧化铵（TMAH）蚀刻材料的方法和设备。 当将TMAH应用于待蚀刻的材料时，该方法可以包括添加剂。 添加剂可以是气体，并且在某些情况下可以是干净的干燥空气。 清洁的干燥空气可以设置有TMAH以最小化或防止在蚀刻结构中形成小丘。 还描述了用于执行方法的装置。

公开(公告)号：US20130147052A1

公开(公告)日：2013-06-13

申请号：US13313397

申请日：2011-12-07

Applicant: Xueren Zhang ,  Kim-Yong Goh

Inventor： Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05092 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05681 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/13027 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.

Abstract translation: 集成电路管芯具有位于集成电路管芯上的所有接触焊盘上的电介质层。 在集成电路管芯的每个接触焊盘上的介电层中设置开口，以便允许在集成电路和管芯外部的电路板之间进行电耦合。 对于位于管芯的中心区域的接触焊盘，电介质层中的开口位于接触焊盘的中心区域。 对于那些位于模具周边区域的接触垫，邻近周边模具间隔开，电介质层中的开口偏离接触焊盘的中心，并且位于比芯片中心更靠近模具的中心区域 接触垫是到模具的中心区域。

公开(公告)号：US20130147024A1

公开(公告)日：2013-06-13

申请号：US13324799

申请日：2011-12-13

Applicant: Kim-Yong GOH ,  Xueren Zhang ,  Wingshenq Wong

Inventor： Kim-Yong GOH ,  Xueren Zhang ,  Wingshenq Wong

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/13 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49861 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion.

Abstract translation: 集成电路封装结构包括具有空腔的底部，连接到阶梯腔的顶表面的集成电路，附接到底部的引线框架，用于将集成电路电耦合到引线框架的引线接合部以及顶部部分 保形地覆盖集成电路和底部。

公开(公告)号：US08451016B2

公开(公告)日：2013-05-28

申请号：US12650257

申请日：2009-12-30

Applicant: Ravi Shankar ,  Olivier Le Neel

Inventor： Ravi Shankar ,  Olivier Le Neel

IPC: G01R31/20 ,  G01R31/00 ,  G01R1/073

CPC classification number: G01R1/07378 ,  G01R1/07342 ,  G01R31/31702 ,  G01R31/318511 ,  G01R31/3278

Abstract: A testing mechanism for testing magnetically operated microelectromechanical system (MEMS) switches at a wafer level stage of manufacture includes an electromagnetic fixture configured to be received in a standard probe ring. The electromagnetic fixture is rotatable, relative to the probe ring, to permit adjustment of orientation of a generated magnetic field relative to the MEMS devices of a subject wafer. The testing mechanism also includes a probe card with probes positioned to contact test pads on the subject wafer. During operation, the probe card is positioned over the wafer to be tested, with the test probes in electrical contact with respective contact pads of the wafer, and the electromagnetic fixture is positioned above the probe card. An electrical potential is applied across the switches on the subject wafer, and the electromagnetic fixture is energized at selected levels of power and duration. Current flow across each switch is measured to determine one or more of: open circuit contact resistance, closed circuit contact resistance, response time, response to switching magnetic field, frequency response, current capacity, critical dimensions, critical angles of magnetic field orientation, etc. Wafer level testing enables rejection of non-compliant switches before the cutting and packaging levels of manufacture.

Abstract translation: 用于在晶片级制造阶段测试磁操作微机电系统（MEMS）开关的测试机构包括被配置为接收在标准探针环中的电磁夹具。 电磁夹具相对于探针环可旋转，以允许相对于目标晶片的MEMS器件调整产生的磁场的取向。 测试机构还包括具有探针的探针卡，所述探针被定位成接触主体晶片上的测试焊盘。 在操作期间，探针卡位于要测试的晶片上，测试探针与晶片的相应接触焊盘电接触，并且电磁夹具位于探针卡上方。 在主体晶片上的开关上施加电势，并且电磁夹具以选定的功率和持续时间被激励。 测量每个开关上的电流，以确定以下一个或多个：开路接触电阻，闭路接触电阻，响应时间，对开关磁场的响应，频率响应，电流容量，临界尺寸，磁场定向的临界角等 晶圆级别测试在切割和封装制造水平之前能够拒绝不符合标准的开关。