公开(公告)号：JP2006286741A

公开(公告)日：2006-10-19

申请号：JP2005101823

申请日：2005-03-31

Applicant: Eudyna Devices Inc ,  Fujitsu Ltd ,  ユーディナデバイス株式会社 ,  富士通株式会社

Inventor： YOKOYAMA MITSUNORI ,  IMANISHI KENJI ,  YOSHIKAWA SHUNEI

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/12

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in performance and reliability by making clear the relationship between an AlN buffer layer and the performance and reliability of a GaN-based FET, its manufacturing method, and a substrate for manufacturing the semiconductor device.
SOLUTION: The semiconductor device is provided with the substrate (10), the buffer layer (12) formed on the substrate (10) and composed of aluminum nitride having a film thickness of 5-40 nm, an operation layer (20) formed on the buffer layer (12) and composed of a gallium nitride-based semiconductor, and a control electrode (26) provided on the operation layer (20). Its manufacturing method, and the substrate for manufacturing the semiconductor device are provided.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供优异的性能和可靠性的半导体器件，通过明确AlN缓冲层与GaN基FET的性能和可靠性之间的关系，其制造方法和制造用基板 半导体器件。 解决方案：半导体器件设置有衬底（10），形成在衬底（10）上并由膜厚度为5-40nm的氮化铝构成的缓冲层（12），操作层（20） ），由氮化镓系半导体构成的缓冲层（12）上形成的控制电极（26）构成。 提供其制造方法和用于制造半导体器件的基板。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006279087A

公开(公告)日：2006-10-12

申请号：JP2006194563

申请日：2006-07-14

Applicant: Eudyna Devices Inc ,  Fujitsu Ltd ,  ユーディナデバイス株式会社 ,  富士通株式会社

Inventor： YAMAMOTO TAKAYUKI ,  SHOJI HAJIME ,  WATANABE TAKAYUKI ,  FUJII TAKUYA ,  KOBAYASHI HIROHIKO

IPC: H01S5/227

Abstract: PROBLEM TO BE SOLVED: To provide a method for realizing a small distance between an active layer and a current block layer with excellent controllability in a buried type semiconductor laser.
SOLUTION: The semiconductor laser includes: a first clad layer made of a compound semiconductor containing an impurity of a first conduction type and provided with a projection of a mesa shape; an active layer formed in a stripe shape on the projection and provided with a side surface inclined in an angle 70 degrees or more and 90 degrees or less to an upper surface of the first clad layer; buried layers formed at both sides of the projection and containing an impurity of a second conduction type; a current block layer containing an impurity of the first conduction type formed on the buried layer and provided with a first surface whose one end contacts with a virtual plane formed by extending side surfaces of the active layer and which is inclined, downward from the contacting end, in an angle of approximately 55 degrees to the upper surface of the first clad layer, and also provided with a second surface which is inclined in an angle larger than that of the side surface of the active layer and smaller than that formed by the upper surface of the first clad layer and a surface perpendicular thereto; and a second clad layer containing an impurity of the second conduction type formed on the current block layer and the active layer.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种在掩埋型半导体激光器中实现具有优异的可控制性的有源层和电流阻挡层之间的小距离的方法。 解决方案：半导体激光器包括：由包含第一导电类型的杂质并且设置有台面形状的突起的化合物半导体制成的第一覆盖层; 在所述突起上形成为带状的有源层，并且具有与所述第一覆盖层的上表面成70度以上且90度以下的角度倾斜的侧面， 形成在突起的两侧并包含第二导电类型的杂质的掩埋层; 包含第一导电类型的杂质的电流阻挡层，其形成在掩埋层上，并且设置有第一表面，该第一表面的一端与由有源层的侧表面延伸形成的虚拟平面接触，该虚拟平面从接触端向下倾斜 与第一覆盖层的上表面成大约55度的角度，并且还设置有第二表面，该第二表面以比活性层的侧表面大的角度倾斜并且小于由上部 第一覆盖层的表面和与其垂直的表面; 以及形成在当前阻挡层和有源层上的包含第二导电类型的杂质的第二包层。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006278580A

公开(公告)日：2006-10-12

申请号：JP2005093275

申请日：2005-03-28

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： IWAGAMI TETSUKAZU

IPC: H01L21/318 ,  C23C16/42 ,  H01L21/338 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/78 ,  H01L29/812

CPC classification number: H01L21/3185 ,  C23C16/345 ,  Y10S438/909 ,  Y10T428/31678

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device with high withstand pressure, a manufacturing method of the device, a capacitor, a manufacturing method of the element, a MIS-type semiconductor device and a manufacturing method of the device. SOLUTION: In the semiconductor device, the capacitor, and the MIS-type semiconductor device; a silicon nitride film 23 formed on the condition that a flow rate with respect to a total flow rate of hydrogen gas is 0.2% to 5% is used for a capacitor film, a passivation film, a gate insulating film or a mask film by using a plasma CVD device and mixed gas formed of mono silane gas, hydrogen gas and nitrogen gas. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了提供具有高耐压的高可靠性半导体器件，该器件的制造方法，电容器，元件的制造方法，MIS型半导体器件和该器件的制造方法 。 解决方案：在半导体器件中，电容器和MIS型半导体器件; 在相对于氢气的总流量为0.2％〜5％的流量的条件下形成的氮化硅膜23用于电容器膜，钝化膜，栅极绝缘膜或掩模膜，通过使用 等离子体CVD装置和由单硅烷气体，氢气和氮气形成的混合气体。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006262218A

公开(公告)日：2006-09-28

申请号：JP2005078314

申请日：2005-03-18

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： NAKANO HIROSHI ,  HIRACHI YASUTAKA

IPC: H01Q13/08 ,  H01Q15/08 ,  H01Q23/00

Abstract: PROBLEM TO BE SOLVED: To solve the problem wherein connection loss between a flat antenna and a transmission line arranged in the thickness direction of a substrate is large.
SOLUTION: The antenna substrate comprises a substrate (10), an antenna portion, and a pseudo coaxial line. The antenna portion is arranged at one plane of the substrate (10), and comprises a first conductor (1) and a second conductor (2), which is arranged separately from and around the first conductor (1) and used as a ground potential. The pseudo coaxial line is arranged in the thickness direction of the substrate (10), and comprises a center conductor (3) connected to the first conductor (1), and a plurality of earth conductors (4) connected to the second conductor (2) and arranged separately from and intermittently around the center conductor (3).
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了解决平板天线与布置在基板的厚度方向上的传输线之间的连接损耗大的问题。 解决方案：天线基板包括基板（10），天线部分和伪同轴线。 天线部分布置在基板（10）的一个平面处，并且包括与第一导体（1）分开设置并且用作接地电位的第一导体（1）和第二导体（2） 。 伪同轴线沿着基板（10）的厚度方向排列，并且包括连接到第一导体（1）的中心导体（3）和连接到第二导体（2）的多个接地导体（4） ）并且围绕中心导体（3）分开设置并间歇地布置。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006261252A

公开(公告)日：2006-09-28

申请号：JP2005074103

申请日：2005-03-15

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KURACHI SHUNSUKE ,  KOMATANI TSUTOMU

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01S5/183

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device for enabling high output operation by reducing a collapse phenomenon without the separation of an insulating layer from a semiconductor layer.
SOLUTION: The semiconductor device comprises a GaN system semiconductor layer 11 formed on a substrate 10, and a silicon nitride film layer formed on the GaN system semiconductor layer to have a silicon/nitrogen composition ratio of 0.8 to 2.5 or an aluminum nitride film layer 20 having an aluminum/silicon composition ratio of 1.0 to 2.5. The manufacturing method of the semiconductor device can improve close contact between the insulating layer and the semiconductor layer by selecting a composition of the silicon nitride layer formed on the semiconductor layer, prevent the separation of the insulating film layer from the surface of semiconductor layer, and reduce the collapse phenomenon.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高可靠性的半导体器件，用于通过减少崩溃现象而实现高输出操作，而不会使绝缘层与半导体层分离。 解决方案：半导体器件包括形成在衬底10上的GaN系半导体层11和形成在GaN系半导体层上以使硅/氮组成比为0.8至2.5的氮化硅膜层或氮化铝 铝/硅组成比为1.0〜2.5的薄膜层20。 半导体器件的制造方法可以通过选择形成在半导体层上的氮化硅层的组成，防止绝缘膜层与半导体层的表面分离来提高绝缘层与半导体层之间的紧密接触，以及 减少崩溃现象。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006229175A

公开(公告)日：2006-08-31

申请号：JP2005044820

申请日：2005-02-21

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： MIYAZAWA NAOYUKI

IPC: H01L25/18 ,  H01L21/822 ,  H01L25/04 ,  H01L27/04 ,  H03M7/00

CPC classification number: H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/49171

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that is easy in manufacturing and inexpensive, a decoder, and a method of manufacturing the same.
SOLUTION: A semiconductor device has a plurality of switches (SP3T10, 13, and SPPT11, 12) each of which has an input pad 16 and an output pad 17 separately, wherein at least part of the plurality of input pads 16 or output pads 17 are configured to be electrically connected to one another externally. At least part of the plurality of input pads 16 or output pads 17 are electrically connected to one another externally in this way, thereby giving a switch configuration according to the specification of apparatus in which the semiconductor device is mounted. Accordingly, the device is easy in manufacturing and inexpensive.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种易于制造和便宜的半导体器件，解码器及其制造方法。 解决方案：半导体器件具有分别具有输入焊盘16和输出焊盘17的多个开关（SP3T10,13和SPPT11,12），其中至少部分多个输入焊盘16或 输出焊盘17被配置为在外部彼此电连接。 多个输入焊盘16或输出焊盘17的至少一部分以这种方式彼此外部电连接，从而根据安装半导体器件的装置的说明书给出开关配置。 因此，该装置制造容易且价廉。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006202781A

公开(公告)日：2006-08-03

申请号：JP2005009635

申请日：2005-01-17

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： AZUMA TOSHIO ,  YAMAUCHI YASUYUKI ,  LE TAILLANDIER DE GABORY EMMAN ,  TANAKA HIROKAZU ,  WATANABE JUNJI

IPC: H01S5/14

Abstract: PROBLEM TO BE SOLVED: To provide a wavelength selection mirror unit that can be miniaturized without making the structure complex.
SOLUTION: The wavelength selection mirror unit 100 comprises a first etalon 10 in which a refractive index to incident light is variable, and a mirror 20 for reflecting incident light through the first etalon. The first etalon 10 is fixed to the mirror 20. In the wavelength selection mirror unit 100, the peak wavelength of incident light can be changed without changing the inclination of the first etalon 10, thus dispensing with space for changing the inclination of the first etalon 10 and hence simplifying the structure of the wavelength selection mirror unit 100. Also, the wavelength selection mirror unit 100 can be miniaturized.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供可以在不使结构复杂的情况下小型化的波长选择镜单元。 解决方案：波长选择镜单元100包括其中入射光的折射率可变的第一标准具10和用于反射通过第一标准具的入射光的反射镜20。 第一标准具10被固定到反射镜20上。在波长选择镜单元100中，可以改变入射光的峰值波长而不改变第一标准具10的倾斜度，从而分配用于改变第一标准具倾斜度的空间 因此简化波长选择镜单元100的结构。此外，波长选择镜单元100可以小型化。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006054723A

公开(公告)日：2006-02-23

申请号：JP2004235552

申请日：2004-08-12

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： MIYAZAWA NAOYUKI

IPC: H03K17/693 ,  H03K19/00

CPC classification number: H04W52/028 ,  Y02D70/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing power consumption.
SOLUTION: The semiconductor device 100 includes a decoder 103 that is connected between a power terminal 5 to which a supply voltage is supplied and a ground terminal 6, and decodes a signal inputted from input terminals 41-43; and a power supply control circuit 109 for disconnecting the power terminal 5 from the decoder 103. The power supply control circuit 109 is connected between the input terminals 41-43 and the decoder 103 in parallel by wire-bonding. The power supply control circuit 109 includes logic 93 for generating a control signal for controlling a drain switch FET 91 by using the combination of signals not used in decoding in the combinations of signals inputted from the input terminals 41-43.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够降低功耗的半导体器件。 解决方案：半导体器件100包括连接在供给电源的电源端子5和接地端子6之间的解码器103，并对从输入端子41-43输入的信号进行解码; 以及用于将电源端子5与解码器103断开的电源控制电路109.电源控制电路109通过引线接合并联连接在输入端子41-43和解码器103之间。 电源控制电路109包括用于通过使用从输入端子41-43输入的信号的组合中的解码中未使用的信号的组合来产生用于控制漏极开关FET91的控制信号的逻辑93。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005353923A

公开(公告)日：2005-12-22

申请号：JP2004174804

申请日：2004-06-11

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： WATANABE KAZUYOSHI

IPC: H01S5/022 ,  H01J3/14 ,  H01L31/02 ,  H01L31/12 ,  H01S5/00 ,  H01S5/02 ,  H01S5/0683

CPC classification number: H01S5/0206 ,  H01L2224/48091 ,  H01S5/005 ,  H01S5/02248 ,  H01S5/0683 ,  H01L2924/00014

Abstract: PROBLEM TO BE SOLVED: To provide a low cost optical module wherein an LD and a surface incident photoreceptor for monitoring the optical output from the LD are mounted on the same substrate. SOLUTION: Wiring 14a-c, 15 for driving the LD 11 and the photoreceptor 12 are formed on the main surface of the platform substrate 13. The rear face of the LD 11 is fixed to the predetermined location of the platform substrate 13, and the photoreceptor 12 is disposed in the rear of the end surface of the LD 11 with the photoreception surface thereof facing upward to be able to monitor the laser beam emitted from the end surface of the LD 11. A reflective part 16 for reflecting the laser beam emitted from the end of the LD 11 to the photoreceptor is provided above the photoreceptor 12. The LD 11 and the photoreceptor 12 are connected to corresponding driving wiring 14a, 15 with bonding wires 17, 18 to form the optical module. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种低成本光学模块，其中LD和用于监测来自LD的光输出的表面入射感光体安装在同一基板上。 解决方案：在平台基板13的主表面上形成用于驱动LD11和感光体12的布线14a-c，15。LD 11的背面固定在平台基板13的预定位置 并且感光体12设置在LD 11的端表面的后面，其光接收表面朝上，以便能够监测从LD 11的端面发射的激光束。反射部分16用于反射 从LD11的端部发射到感光体的激光束设置在感光体12的上方.LD11和感光体12通过接合线17,18与相应的驱动配线14a，15连接，形成光模块。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005322811A

公开(公告)日：2005-11-17

申请号：JP2004140431

申请日：2004-05-10

Applicant: Eudyna Devices Inc ,  ユーディナデバイス株式会社

Inventor： KOMATANI TSUTOMU

IPC: H01L21/28 ,  H01L21/00 ,  H01L21/033 ,  H01L21/04 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/338 ,  H01L21/461 ,  H01L21/768 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0475 ,  H01L21/3081

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing GaN based semiconductor devices for high precision processes, by improving the adhesion of mask for dry etching to the surface of etching material.
SOLUTION: A Ti film 22 and an Ni film 24 are laminated, in this order, on a GaN-based semiconductor layer of etching material and a substrate 21 of SiC or sapphire, for film formation by vacuum deposition. The laminated film is patterned by photolithographic method to form a mask. If the etching base body is, for example, the SiC substrate, the thermal expansion coefficient of SiC is 4.2×10
-6 /°C and that of Ni is 12.8×10
-6 /°C. By providing the Ti film 22, whose thermal expansion coefficient is 9.0×10
-6 /°C, the distortion generated by thermal expansion due to the rise of the temperature during etching is reduced to improve adhesion of the mask to the SiC substrate surface, resulting in suppressing of the occurrence of peeling or cracking.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造用于高精度工艺的GaN基半导体器件的方法，通过改善用于干蚀刻的掩模与蚀刻材料的表面的粘附。 解决方案：依次将Ti膜22和Ni膜24层叠在蚀刻材料的GaN基半导体层和SiC或蓝宝石的衬底21上，用于通过真空沉积成膜。 通过光刻法将层压膜图案化以形成掩模。 如果蚀刻基体是例如SiC基板，则SiC的热膨胀系数为4.2×10 -6 /℃，Ni的热膨胀系数为12.8×10 -6 < / SP> /℃。 通过设置其热膨胀系数为9.0×10 -6 /℃的Ti膜22，由于蚀刻期间的温度上升而由热膨胀产生的变形减小，以提高 掩模到SiC衬底表面，导致抑制剥离或开裂的发生。 版权所有（C）2006，JPO＆NCIPI