公开(公告)号：US09954071B2

公开(公告)日：2018-04-24

申请号：US15174720

申请日：2016-06-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES ,  Jiangnan University

Inventor： Yuqiang Ding ,  Chao Zhao ,  Jinjuan Xiang

IPC: C23C16/00 ,  H01L29/49 ,  C23C16/02 ,  C23C16/08 ,  C23C16/18 ,  C23C16/455 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/4966 ,  C23C16/0209 ,  C23C16/08 ,  C23C16/18 ,  C23C16/45527 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.

公开(公告)号：US09953923B2

公开(公告)日：2018-04-24

申请号：US15462475

申请日：2017-03-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L23/5222 ,  H01L27/0629

Abstract: A metallization stack, comprising: at least an interlayer dielectric layer comprising a dielectric material and a negative capacitance material, wherein: at least a pair of first conductive interconnecting components formed in the interlayer dielectric layer, which are at least partially opposite to each other, comprise both the dielectric material and the negative capacitance material sandwiched between their opposite parts; and/or at least a second conductive interconnecting component formed in an upper interlayer dielectric layer and at least a third conductive interconnecting component formed in a lower interlayer dielectric layer, which are at least partially opposite to each other, comprise both the dielectric material and the negative capacitance material sandwiched between their opposite parts.

公开(公告)号：US20180108577A1

公开(公告)日：2018-04-19

申请号：US15722423

申请日：2017-10-02

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhengyong Zhu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/822 ,  H01L21/308

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

公开(公告)号：US20180097106A1

公开(公告)日：2018-04-05

申请号：US15720240

申请日：2017-09-29

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/15 ,  H01L29/165 ,  H01L29/08 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/324 ,  H01L29/778

CPC classification number: H01L21/823885 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/2252 ,  H01L21/2258 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/324 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/152 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/78642

Abstract: A semiconductor device, a method of manufacturing the same and an electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device may include a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a channel region close to its peripheral surface and a body region disposed on an inner side of the channel region.

公开(公告)号：US20180097065A1

公开(公告)日：2018-04-05

申请号：US15718586

申请日：2017-09-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02

Abstract: There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

公开(公告)号：US09899270B2

公开(公告)日：2018-02-20

申请号：US14233320

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Qiuxia Xu ,  Huilong Zhu ,  Gaobo Xu ,  Huajie Zhou ,  Qingqing Liang ,  Dapeng Chen ,  Chao Zhao

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

公开(公告)号：US09773707B2

公开(公告)日：2017-09-26

申请号：US14838628

申请日：2015-08-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guilei Wang ,  Jinbiao Liu ,  Jianfeng Gao ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215

CPC classification number: H01L21/823828 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/7845

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

公开(公告)号：US09762217B2

公开(公告)日：2017-09-12

申请号：US14888335

申请日：2013-07-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Dongmei Li ,  Qing Luo ,  Shengfa Liang ,  Hongzhang Yang ,  Xiaojing Li ,  Hao Zhang ,  Changqing Xie ,  Ming Liu

IPC: H03K4/08 ,  A61B5/00 ,  H03K3/84 ,  H03K4/50

CPC classification number: H03K4/08 ,  A61B5/00 ,  H03K3/84 ,  H03K4/50

Abstract: A sampler adapted to a one-dimension slow-varying signal, including: a signal preprocessing unit configured to preprocess an input signal; a slope-controllable sawtooth wave signal generating unit configured to generate a slope-controllable sawtooth wave signal and perform zero-resetting; a signal comparing unit configured to compare the preprocessed input signal from the signal preprocessing unit with the sawtooth wave signal and to output a pulse signal to the generating unit and a signal outputting unit when the preprocessed input signal is equal to the sawtooth wave signal; a counting unit configured to count a number of clock signals while the sawtooth wave signal generating unit is generating the sawtooth wave signal and to transmit the counted number to the signal outputting unit; the signal outputting unit configured to, upon receipt of the pulse signal output from the signal comparing unit, output the number counted by the counting unit at the moment.

公开(公告)号：US20170250193A1

公开(公告)日：2017-08-31

申请号：US15311000

申请日：2014-07-10

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Zongliang HUO

IPC: H01L27/11582 ,  H01L21/324

CPC classification number: H01L27/11582 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/40117

Abstract: A method of manufacturing three-dimensional semiconductor device, comprising the steps of: forming a stack structure of a plurality of a first material layers and a second material layers on a substrate in the memory cell region; etching said stack structure to form a plurality of trenches; forming channel layers in said plurality of trenches; performing annealing treatment to at least one surface of the channel layers to reduce the surface roughness and the interface state. In accordance with the three-dimensional semiconductor device manufacturing method of the present invention, the formation of interface states is depressed by introducing a dummy channel sacrificial layer for the interface treatment on the channel surface and back surface, and/or the channel surface roughness is reduced by introducing a buffer layer on the channel surface and back surface during the treatment, which can improve the channel carrier mobility, improve the channel current as well as the reliability of the memory cell.

公开(公告)号：US09748141B2

公开(公告)日：2017-08-29

申请号：US14441369

申请日：2012-11-19

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66545

Abstract: Provided are a semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate, wherein the first semiconductor layer is doped; patterning the second and first semiconductor layers to form an initial fin; forming a dielectric layer on the substrate to substantially cover the initial fin, wherein a portion of the dielectric layer on top of the initial fin has a thickness sufficiently less than that of a portion of the dielectric layer on the substrate; etching the dielectric layer back to form an isolation layer, wherein the isolation layer partially exposes the first semiconductor layer, thereby defining a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.